Se-Hyun Yang

Dynamically Resizable Instruction Cache: An Energy-Efficient and High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000 .

Power-aware High-performance Cache Memory in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

Se-Hyun Yang, 2003 .

Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Babak Falsafi, T. N. Vijaykumar, Se-Hyun Yang, 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

A 32nm high-k metal gate application processor with GHz multi-core CPU

Jae Young Lee, Youngmin Shin, Seung Ho Hwang, 2012, 2012 IEEE International Solid-State Circuits Conference.

Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

T. N. Vijaykumar, Se-Hyun Yang, K. Roy, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000, ISLPED '00.

Accurate and complexity-effective spatial pattern prediction

Babak Falsafi, Andreas Moshovos, Chi F. Chen, 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

Reducing leakage in a high-performance deep-submicron instruction cache

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

An Energy-Efficient High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2001 .

Evaluating Opportunity and Effectiveness of Cache Resizing in Reducing Energy Dissipation

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001 .