Srinivasan Murali

发表

Early wire characterization for predictable network-on-chip global interconnects

Stéphane Badel, Yusuf Leblebici, Srinivasan Murali, 2007, SLIP '07.

Routing Aware Switch Hardware Customization for Networks on Chips

Srinivasan Murali, Giovanni De Micheli, Paolo Meloni, 2006, 2006 1st International Conference on Nano-Networks and Workshops.

Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea

Srinivasan Murali, David Atienza, Grégoire Surrel, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Method for Integrating Network-on-Chip Topologies with 3D ICs

Luca Benini, Srinivasan Murali, M. Pawan Kumar, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

A method for calculating hard QoS guarantees for Networks-on-Chip

Luca Benini, Dara Rahmati, Srinivasan Murali, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Analysis of error recovery schemes for networks on chips

Luca Benini, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, IEEE Design & Test of Computers.

A wearable device for physical and emotional health monitoring

Srinivasan Murali, David Atienza, Francisco J. Rincón, 2015, 2015 Computing in Cardiology Conference (CinC).

Designing Application-Specific Networks on Chips with Floorplan Information

Luca Benini, Srinivasan Murali, Federico Angiolini, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Luca Benini, Srinivasan Murali, David Atienza, 2009, CODES+ISSS '09.

NoC Support for Reliable On-Chip Memories

Srinivasan Murali, 2009 .

Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone

Srinivasan Murali, David Atienza, Francisco J. Rincón, 2015, 2015 Euromicro Conference on Digital System Design.

Performance driven reliable link design for networks on chips

Srinivasan Murali, Giovanni De Micheli, Rutuparna Tamhankar, 2005, ASP-DAC.

A DRAM Centric NoC Architecture and Topology Design Approach

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Timing-Error-Tolerant Network-on-Chip Design Methodology

Luca Benini, Srinivasan Murali, Federico Angiolini, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Application-Specific Design Methodology for STbus Crossbar Generation

Srinivasan Murali, Giovanni De Micheli, 2005, Design, Automation and Test in Europe.

Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimation

Srinivasan Murali, David Atienza, Dionisije Sopic, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

Srinivasan Murali, Giovanni De Micheli, Kees G. W. Goossens, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

Synthesis of networks on chips for 3D systems on chips

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2009, 2009 Asia and South Pacific Design Automation Conference.

Mapping and configuration methods for multi-use-case networks on chips

Srinivasan Murali, Giovanni De Micheli, Kees G. W. Goossens, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A Methodology for Mapping Multiple Use-Cases onto Networks on Chips

Srinivasan Murali, Giovanni De Micheli, Kees G. W. Goossens, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Luca Benini, Srinivasan Murali, Federico Angiolini, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

SUNMAP: a tool for automatic topology selection and generation for NoCs

Srinivasan Murali, Giovanni De Micheli, 2004, Proceedings. 41st Design Automation Conference, 2004..

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2009, DATE.

Designing Reliable and Efficient Networks on Chips

Srinivasan Murali, S. Murali, 2009, Lecture Notes in Electrical Engineering.

Design of Networks on Chips for 3D ICs

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Design of ultra-low-power smart wearable systems

Srinivasan Murali, David Atienza, Grégoire Surrel, 2015, 2015 16th Latin-American Test Symposium (LATS).

Processor Speed Control With Thermal Constraints

Stephen P. Boyd, Srinivasan Murali, Giovanni De Micheli, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Application-Specific Design Methodology for On-Chip Crossbar Generation

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Designing Routing and Message-Dependent Deadlock Free Networks on Chips

Luca Benini, Srinivasan Murali, Federico Angiolini, 2006, VLSI-SoC.

Bringing NoCs to 65nm

Srinivasan Murali, Federico Angiolini, Giovanni De Micheli, 2007 .

Bandwidth-constrained mapping of cores onto NoC architectures

Srinivasan Murali, Giovanni De Micheli, G. Micheli, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Timing-Error Tolerant NoC Design

Srinivasan Murali, 2009 .

NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2009, 2009 46th ACM/IEEE Design Automation Conference.

A Simulation Based Buffer Sizing Algorithm for Network on Chips

Luca Benini, V. Kamakoti, Srinivasan Murali, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Reliability Support for On-Chip Memories Using Networks-on-Chip

Luca Benini, Srinivasan Murali, Federico Angiolini, 2006, 2006 International Conference on Computer Design.

NoC Design and Implementation in 65nm Technology

Luca Benini, Srinivasan Murali, Federico Angiolini, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

Real-time probabilistic heart beat classification and correction for embedded systems

Srinivasan Murali, David Atienza, Grégoire Surrel, 2015, 2015 Computing in Cardiology Conference (CinC).

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2011, 3D Integration for NoC-based SoC Architectures.

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Supporting Dynamic Application Patterns

Srinivasan Murali, 2009 .

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization

Luca Benini, Stephen P. Boyd, Srinivasan Murali, 2008, 2008 Design, Automation and Test in Europe.

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Luca Benini, Srinivasan Murali, Federico Angiolini, 2006, 2006 International Symposium on System-on-Chip.

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2011, Low Power Networks-on-Chip.

Ultra-low power design of wearable cardiac monitoring systems

Srinivasan Murali, David Atienza, Francisco J. Rincón, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Timing-Error-Tolerant Network-on-Chip

Srinivasan Murali, Federico Angiolini, Stergios Stergiou, 2007 .

Network-on-Chip design and synthesis outlook

Luca Benini, Srinivasan Murali, Federico Angiolini, 2008, Integr..

Designing best effort networks-on-chip to meet hard latency constraints

Luca Benini, Dara Rahmati, Srinivasan Murali, 2013, TECS.

Ultra-Low Power Estimation of Heart Rate Under Physical Activity Using a Wearable Photoplethysmographic System

Srinivasan Murali, David Atienza, Francisco J. Rincón, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Temperature-aware processor frequency assignment for MPSoCs using convex optimization

Stephen P. Boyd, Srinivasan Murali, Giovanni De Micheli, 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Methods for reliable estimation of pulse transit time and blood pressure variations using smartphone sensors

Srinivasan Murali, David Atienza, Francisco J. Rincón, 2016, Microprocess. Microsystems.

Diseño de redes en chip de propósito específico con información de rutado físico

Srinivasan Murali, Federico Angiolini, Giovanni De Micheli, 2006 .

Networks on Chips: From research to products

Luca Benini, Srinivasan Murali, Federico Angiolini, 2010, Design Automation Conference.

Quality-of-Service in NoCs

Srinivasan Murali, Federico Angiolini, 2018 .

Network-on-Chips on 3-D ICs: Past, Present, and Future

Kamakoti Veezhinathan, Srinivasan Murali, M. Pawan Kumar, 2012 .

Bringing NoCs to 65 nm

Luca Benini, Srinivasan Murali, Federico Angiolini, 2007, IEEE Micro.

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2007, VLSI Design.

Energy-aware embedded classifier design for real-time emotion analysis

Srinivasan Murali, David Atienza, Francisco J. Rincón, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2005, IEEE Transactions on Parallel and Distributed Systems.

A floorplan-aware interactive tool flow for NoC design and synthesis

Luca Benini, Srinivasan Murali, Federico Angiolini, 2009, 2009 IEEE International SOC Conference (SOCC).

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands

Luca Benini, V. Kamakoti, Srinivasan Murali, 2012, J. Electr. Comput. Eng..

Online Obstructive Sleep Apnea Detection on Medical Wearable Sensors

Srinivasan Murali, David Atienza, Amir Aminifar, 2018, IEEE Transactions on Biomedical Circuits and Systems.

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Periscope: A Keystroke Inference Attack Using Human Coupled Electromagnetic Emanations

Srinivasan Murali, Wenqiang Jin, Huadi Zhu, 2021, CCS.

Optimized Slowdown in Real-Time Task Systems via Geometric Programming

Srinivasan Murali, Giovanni De Micheli, Stephen Boyd, 2007 .