Gia Vinh Luong

Static noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices

Michael Graef, Benjamín Iñíguez, Fabian Horst, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation

Michael Graef, Benjamín Iñíguez, Fabian Horst, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Si n-TFETs on ultra thin body with suppressed ambipolarity

Xi Wang, Chang Liu, Qinghua Han, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM

Pierpaolo Palestri, Sebastiano Strangio, Siegfried Mantl, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages

Sebastiano Strangio, Gia Vinh Luong, Qing-Tai Zhao, 2016 .

Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V

Lars Knoll, Siegfried Mantl, Gia Vinh Luong, 2014, 72nd Device Research Conference.