Katsuaki Isobe

13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology

Hiroshi Nakamura, Lei Lin, Minoru Yamashita, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Khanh Nguyen, W. Igarashi, A. Inoue, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)

Satoshi Eto, Katsuaki Isobe, H. Toda, 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface

Hong Ding, Manabu Sato, Takeshi Ogawa, 2012, 2012 IEEE International Solid-State Circuits Conference.

A novel analog mirror type DLL suitable for low voltage operation with self-calibration method

Satoshi Eto, Katsuaki Isobe, Kenji Tsuchida, 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

A 19 nm 112.8 mm$^{2}$ 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

Hong Ding, Manabu Sato, Takeshi Ogawa, 2013, IEEE Journal of Solid-State Circuits.