Yun-Nan Chang

发表

A Fast Spline Curve Rendering Accelerator Architecture

Yun-Nan Chang, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

An integrated HDTV predictive pixel compensator for H.264/AVC decoder

Yun-Nan Chang, Ting-Chi Tong, 2011, 2011 IEEE International Conference on IC Design & Technology.

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics

Ing-Jer Huang, Liang-Bi Chen, Chien-Chou Wang, 2009, 2009 Asia and South Pacific Design Automation Conference.

A fast ray tracing scheme for dynamic scenes

Yun-Nan Chang, Chin-Lun Yang, 2017, 2017 4th International Conference on Control, Decision and Information Technologies (CoDIT).

A low-cost dual-mode deinterleaver design

Yun-Nan Chang, 2008, IEEE Transactions on Consumer Electronics.

Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination

Yun-Nan Chang, Guan-Jhen Chen, Yun-Nan Chang, 2019, 2019 International Conference on Electronics, Information, and Communication (ICEIC).

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics

Ing-Jer Huang, Chien-Chou Wang, Jin-Hua Hong, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Lower-Power Viterbi Decoder Design Methodology Based on Dynamic Survivor Path Decision

Yun-Nan Chang, Yu-Chung Ding, 2006, 2006 International Symposium on VLSI Design, Automation and Test.

Design of Viterbi decoders with in-place state metric update and hybrid traceback processing

Yun-Nan Chang, Ching-Wen Wang, 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator

Yun-Nan Chang, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Loop-list scheduling for heterogeneous functional units

Keshab K. Parhi, Ching-Yi Wang, Yun-Nan Chang, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

High-performance digit-serial complex-number multiplier-accumulator

Keshab K. Parhi, Yun-Nan Chang, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Architectures for digital filters using stochastic computing

Keshab K. Parhi, Yun-Nan Chang, 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers

Keshab K. Parhi, Yun-Nan Chang, Leilei Song, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Low-power digit-serial and bit-serial dsp systems

Keshab K. Parhi, Yun-Nan Chang, 1999 .

The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control

Ing-Jer Huang, Shiann-Rong Kuang, Liang-Bi Chen, 2008, 2008 International SoC Design Conference.

An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering

Yun-Nan Chang, Ting-Chi Tong, Yun-Nan Chang, 2015, J. Signal Process. Syst..

Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems

Keshab K. Parhi, Hiroshi Suzuki, Yun-Nan Chang, 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

An efficient hardware-software codesign of 3D rasterization module

Yun-Nan Chang, 2011, 2011 IEEE International Conference on Consumer Electronics -Berlin (ICCE-Berlin).

A four-bank memory design of optimized semi-parallel polar decoder

Liang Chen, Yun-Nan Chang, Shiwen Xing, 2017, 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN).

Scaling Bit-Flexible Neural Networks

Yun-Nan Chang, Yu-Tang Tin, 2019, 2019 International SoC Design Conference (ISOCC).

Design of soft-output Viterbi decoders with hybrid trace-back processing

Yun-Nan Chang, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Two-level hierarchical fill-buffer for graphics rendering systems

Yun-Nan Chang, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

Digit-Serial Pipeline Sorter Architecture

Yun-Nan Chang, 2010, J. Signal Process. Syst..

A low cost 2D graphics anti-aliasing rendering scheme

Yun-Nan Chang, Ting-Chi Tong, 2010, 2010 International Symposium on Next Generation Electronics.

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

Yun-Nan Chang, Yun-Nan Chang, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer

Yun-Nan Chang, Ting-Chi Tong, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of an efficient memory-based DVB-T channel decoder

Yun-Nan Chang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Design of a 2D graphics front-end rendering processor

Yun-Nan Chang, Ting-Chi Tong, 2014, 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors.

An Efficient VLSI Architecture for Normal I/O Order

Yun-Nan Chang, 2008 .

Systematic design of high-speed and low-power digit-serial multipliers

Keshab K. Parhi, Yun-Nan Chang, J. H. Satyanarayana, 1998 .

An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization

Yun-Nan Chang, Ting-Chi Tong, 2007, 2007 Digest of Technical Papers International Conference on Consumer Electronics.

AIoTs for Smart Shrimp Farming

Ing-Jer Huang, Shiann-Rong Kuang, Yun-Nan Chang, 2019, 2019 International SoC Design Conference (ISOCC).

A Lossless Buffer Compression Scheme for 3D Graphic System

Yun-Nan Chang, Ting-Chi Tong, 2009, CGVR.

$Q2SHQ*/(6'*UDSKLFV6R&ZLWK9HUVDWLOH+:6: 'HYHORSPHQW6XSSRUW

Yun-Nan Chang, Shen-Fu Hsiao, Kai-Hsiang Tsao, 2015 .

Design and implementation of low-power digit-serial multipliers

Keshab K. Parhi, Yun-Nan Chang, Janardhan H. Satyanarayana, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Design of highly efficient VLSI architectures for 2-D DWT and 2-D IDWT

Yun-Nan Chang, Yan-Sheng Li, 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support

Chun-Hung Lai, Ing-Jer Huang, Shiann-Rong Kuang, 2015, VLSI Design, Automation and Test(VLSI-DAT).

An Efficient Design of H.264 Inter Interpolator

Yun-Nan Chang, Hsin-Yu Lin, 2007 .

An Efficient In-Place VLSI Architecture for Viterbi Algorithm

Yun-Nan Chang, 2003, J. VLSI Signal Process..

An edge-list compression scheme for 2-D graphic system

Yun-Nan Chang, Ting-Chi Tong, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver

Yun-Nan Chang, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of an 8192-point Sequential I / O FFT Chip

Yun-Nan Chang, 2012 .

Low-power digit-serial multipliers

Keshab K. Parhi, Yun-Nan Chang, J. H. Satyanarayana, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.