Robert Gauthier

发表

Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

Souvick Mitra, Junjun Li, Robert Gauthier, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations

Souvick Mitra, Junjun Li, Robert Gauthier, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

Novel ESD Compact Modeling Methodology Using Machine Learning Techniques

Souvick Mitra, Robert Gauthier, Wei Liang, 2020, 2020 42nd Annual EOS/ESD Symposium (EOS/ESD).

Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology

Robert Gauthier, Tom Herrmann, Alban Zaka, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Influence of Package Trace Properties on CDM Stress

Robert Gauthier, Bill Reynolds, James P. Di Sarro, 2014, IEEE Transactions on Device and Materials Reliability.

Junction engineering for SOI SCR triggering and performance improvement

Junjun Li, Robert Gauthier, You Li, 2014, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014.

An ESD design automation framework and tool flow for nano-scale CMOS technologies

Souvick Mitra, Junjun Li, Robert Gauthier, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

Identification and verification of BEOL metal fails due to ESD stress using current density analysis tool

Souvick Mitra, Robert Gauthier, Ralph Halbach, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Junjun Li, Robert Gauthier, Ralph Halbach, 2006, Microelectron. Reliab..

Reflection control in VF-TLP systems

Evan Grund, Robert Gauthier, Justin Katz, 2014, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014.

3D integration ESD protection design and analysis

Souvick Mitra, Katsuyuki Sakuma, Robert Gauthier, 2015, 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Influence of package parasitic elements on CDM stress

Robert Gauthier, James Di Sarro, Bill Reynold, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

3-D Integration and ESD Protection: Design and Analysis

Souvick Mitra, Robert Gauthier, You Li, 2016, IEEE Transactions on Device and Materials Reliability.

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Junjun Li, Davood Shahrjerdi, Robert Gauthier, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies

Junjun Li, Yang Yang, Robert Gauthier, 2011, EOS/ESD Symposium Proceedings.

Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation

Souvick Mitra, Junjun Li, Robert Gauthier, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies

Robert Gauthier, You Li, Meng Miao, 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).

A current density analysis tool to identify BEOL fails under ESD stress

Souvick Mitra, Robert Gauthier, Ralph Halbach, 2011, EOS/ESD Symposium Proceedings.

Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node

Souvick Mitra, Aihua Dong, Robert Gauthier, 2018, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network

Junjun Li, Robert Gauthier, Shunhua Chang, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Activities towards a new transient latch-up standard

Nate Peachey, Robert Gauthier, Alan Righter, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp

Robert Gauthier, Milova Paul, Vishal Ganesan, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

A New CDM Discharge Head for Increased Repeatability and Testing Small Pitch Packages

Evan Grund, Robert Gauthier, Chad Burke, 2018, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

External Latchup Risks and Prevention Solutions in Advanced Bulk FinFET Technology

Souvick Mitra, Robert Gauthier, Wei Liang, 2019, 2019 41st Annual EOS/ESD Symposium (EOS/ESD).

ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Souvick Mitra, Robert Gauthier, Elyse Rosenbaum, 2009, 2009 31st EOS/ESD Symposium.

Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions

Robert Gauthier, James Di Sarro, Junjun Li, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.