Ralph Halbach

Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

Souvick Mitra, Junjun Li, Robert Gauthier, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

Identification and verification of BEOL metal fails due to ESD stress using current density analysis tool

Souvick Mitra, Robert Gauthier, Ralph Halbach, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Junjun Li, Robert Gauthier, Ralph Halbach, 2006, Microelectron. Reliab..

Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Junjun Li, Ralph Halbach, Christian Russ, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

A current density analysis tool to identify BEOL fails under ESD stress

Souvick Mitra, Robert Gauthier, Ralph Halbach, 2011, EOS/ESD Symposium Proceedings.

Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network

Junjun Li, Robert Gauthier, Shunhua Chang, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.