M. Annese

Design and optimization of a hot-carrier resistant high-voltage nMOS transistor

M. Annese, S. Carniello, S. Manzini, 2005, IEEE Transactions on Electron Devices.

0.18 μm BCD -High Voltage Gate (HVG) Process to address Advanced Display Drivers Roadmap

C. Contiero, P. Galbiati, M. Annese, 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..