Zdenek Kotásek

发表

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties

Zdenek Kotásek, Lukás Sekanina, Tomas Pecenka, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Comparison of FPNNs models approximation capabilities and FPGA resources utilization

Jakub Lojda, Zdenek Kotásek, Martin Krcma, 2017, 2017 13th IEEE International Conference on Intelligent Computer Communication and Processing (ICCP).

Testability Estimation Based on Controllability and Observability Parameters

Zdenek Kotásek, Lukás Sekanina, Josef Strnadel, 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

RT level testability analysis to reduce test application time

Zdenek Kotásek, F. Zboril, 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

Triple modular redundancy used in field programmable neural networks

Jakub Lojda, Zdenek Kotásek, Martin Krcma, 2017, 2017 IEEE East-West Design & Test Symposium (EWDTS).

SET: interactive tool for learning and training scan-based DFT principles and their consequences to parameters of embedded system

Zdenek Kotásek, Josef Strnadel, 2006, 13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06).

Advanced fault tolerant bus for multicore system implemented in FPGA

Zdenek Kotásek, Jaroslav Novotný, Martin Straka, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Checker Design for On-line Testing of Xilinx FPGA Communication Protocols

Zdenek Kotásek, Martin Straka, Jiri Tobola, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery

Zdenek Kotásek, Karel Szurman, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Data types and operations modifications: A practical approach to fault tolerance in HLS

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek, 2017, 2017 IEEE East-West Design & Test Symposium (EWDTS).

The Use of Genetic Algorithm to Reduce Power Consumption during Test Application

Zdenek Kotásek, Josef Strnadel, Jaroslav Skarvada, 2010, ICES.

State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

Zdenek Kotásek, Karel Szurman, Lukas Miculka, 2014, 2014 17th Euromicro Conference on Digital System Design.

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430

Zdenek Kotásek, Karel Szurman, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Detecting hard synapses faults in artificial neural networks

Jakub Lojda, Zdenek Kotásek, Martin Krcma, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Application of Evolutionary Algorithms for Regression Suites Optimization

Zdenek Kotásek, Michaela Beleova, Marcela Simková, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Software Fault Tolerance: The Evaluation by Functional Verification

Jakub Podivinsky, Ondrej Cekan, Zdenek Kotásek, 2015, 2015 Euromicro Conference on Digital System Design.

HLS-based fault tolerance approach for SRAM-based FPGAs

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Zdenek Kotásek, Jaroslav Skarvada, Tomas Herrman, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Zdenek Kotásek, Martin Straka, Jan Kastil, 2011, 2011 14th Euromicro Conference on Digital System Design.

Random stimuli generation based on a stochastic context-free grammar

Jakub Podivinsky, Ondrej Cekan, Zdenek Kotásek, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis

Zdenek Kotásek, Marcela Zachariásová, Michaela Kekelyova-Beleova, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Digital Systems Architectures Based on On-line Checkers

Zdenek Kotásek, Martin Straka, Jan Winter, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Automation and Optimization of Coverage-driven Verification

Zdenek Kotásek, Marcela imkova, Z. Kotásek, 2015, 2015 Euromicro Conference on Digital System Design.

Automatic Construction of On-line Checking Circuits Based on Finite Automata

Zdenek Kotásek, Jan Kastil, Lucie Matuova, 2014, 2014 17th Euromicro Conference on Digital System Design.

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Zdenek Kotásek, Martin Straka, Jan Kastil, 2012, 2012 15th Euromicro Conference on Digital System Design.

Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits

Zdenek Kotásek, Josef Strnadel, Tomas Pecenka, 2008, Comput. Informatics.

Test platform for fault tolerant systems design properties verification

Zdenek Kotásek, Martin Straka, Jan Kastil, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Testability analysis based on the identification of testable blocks with predefined properties

Zdenek Kotásek, Jaroslav Skarvada, Tomas Herrman, 2008, Microprocess. Microsystems.

Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage

Zdenek Kotásek, Lukás Sekanina, Zbysek Gajda, 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area

Zdenek Kotásek, Martin Straka, Lukas Miculka, 2013, 2013 Euromicro Conference on Digital System Design.

Program Generation Through a Probabilistic Constrained Grammar

Jakub Podivinsky, Ondrej Cekan, Zdenek Kotásek, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Mapping Trained Neural Networks to FPNNs

Zdenek Kotásek, Martin Krcma, Jan Kastil, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Functional verification based platform for evaluating fault tolerance properties

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2017, Microprocess. Microsystems.

Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA

Zdenek Kotásek, Lukas Miculka, Z. Kotásek, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Novel Logic Circuits Controlled by Vdd

Zdenek Kotásek, Lukás Sekanina, Lukás Starecek, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Test scheduling for embedded systems

Zdenek Kotásek, Josef Strnadel, Daniel Mika, 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek, 2017, 2017 IEEE East-West Design & Test Symposium (EWDTS).

Automated Functional Verification of Application Specific Instruction-set Processors

Zdenek Kotásek, Zdenek Prikryl, Tomás Hruska, 2013, IESS.

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Zdenek Kotásek, Martin Straka, Jan Kastil, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek, 2019, 2019 IEEE Latin American Test Symposium (LATS).

pecial CAI Section Devoted to MEMICS '11: Preface

Jan Bouda, Ivana Cerná, Zdenek Kotásek, 2012, Comput. Informatics.

Analysis and comparison of functional verification and ATPG for testing design reliability

Zdenek Kotásek, Cristiana Bolchini, Marcela Simková, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

The Identification of registers in RTL Structures for the Test Application

Zdenek Kotásek, Josef Strnadel, Daniel Mika, 2004, ISoLA.

Testability improvements based on the combination of analytical and evolutionary approaches at RT level

Zdenek Kotásek, Josef Strnadel, 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

FPGA Prototyping and Accelerated Verification of ASIPs

Jakub Podivinsky, Ondrej Cekan, Zdenek Kotásek, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Zdenek Kotásek, Lukás Sekanina, Lukás Starecek, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

A Probabilistic Context-Free Grammar Based Random Test Program Generation

Ondrej Cekan, Zdenek Kotásek, 2017, 2017 Euromicro Conference on Digital System Design (DSD).

Variable byte-length data compression algorithm

Zdenek Kotásek, Martin Straka, Jan Kastil, 2010, 2010 12th Biennial Baltic Electronics Conference.

The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications

Jakub Podivinsky, Ondrej Cekan, Zdenek Kotásek, 2014, DSD.

Automatic discovery of RTL benchmark circuits with predefined testability properties

Zdenek Kotásek, Lukás Sekanina, Josef Strnadel, 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

RT level test scheduling

Zdenek Kotásek, Jan Hlavicka, J. Blatný, 1993, Proceedings ETC 93 Third European Test Conference.

Reliability Analysis and Improvement of FPGA-Based Robot Controller

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2017, 2017 Euromicro Conference on Digital System Design (DSD).

Preface

Zdenek Kotásek, Ludek Matyska, Milan Ceska, 2009, Electron. Notes Theor. Comput. Sci..

I-path analysis

Zdenek Kotásek, J. Blatný, J. Blatný, 1993, Proceedings ETC 93 Third European Test Conference.

High Availability Fault Tolerant Architectures Implemented into FPGAs

Zdenek Kotásek, Martin Straka, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Polymorphic Gates in Design and Test of Digital Circuits

Zdenek Kotásek, Lukás Sekanina, Zbysek Gajda, 2008, Int. J. Unconv. Comput..

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Zdenek Kotásek, Josef Strnadel, Jaroslav Skarvada, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Online Protocol Testing for FPGA Based Fault Tolerant Systems

Zdenek Kotásek, Tomás Martínek, Jan Korenek, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Reduction of power dissipation through parallel optimization of test vector and scan register sequences

Zdenek Kotásek, Josef Strnadel, Jaroslav Skarvada, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Evolution of synthetic RTL benchmark circuits with predefined testability

Zdenek Kotásek, Lukás Sekanina, Tomas Pecenka, 2008, TODE.

Educational tool for the demonstration of DfT principles based on scan methodologies

Zdenek Kotásek, Josef Strnadel, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Decreasing test time by scan chain reorganization

Zdenek Kotásek, Pavel Bartos, Jan Dohnal, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Fault tolerant Field Programmable Neural Networks

Zdenek Kotásek, Martin Krcma, Jan Kastil, 2015, 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

Implementation of fault tolerant techniques into FPNNs

Jakub Lojda, Zdenek Kotásek, Martin Krcma, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications

Jakub Podivinsky, Ondrej Cekan, Zdenek Kotásek, 2014, 2014 17th Euromicro Conference on Digital System Design.

Power Conscious RTL Test Scheduling

Zdenek Kotásek, Jaroslav Skarvada, Tomas Herrman, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Fault tolerant CAN bus control system implemented into FPGA

Zdenek Kotásek, Martin Straka, Jan Kastil, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs

Jakub Lojda, Zdenek Kotásek, Richard Panek, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

Testing Embedded Software Through Fault Injection: Case Study on Smart Lock

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, 2021, 2021 IEEE 22nd Latin American Test Symposium (LATS).

Reliability Analysis of the FPGA Control System with Reconfiguration Hardening

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery

Jakub Lojda, Zdenek Kotásek, Richard Panek, 2021, 2021 IEEE East-West Design & Test Symposium (EWDTS).