K. Barla

发表

Jerome Mitard, Rita Rooyackers, Anne Vandooren, 2015 .

Patterning challenges in advanced device architectures: FinFETs to nanowires

L. Witters, N. Waldron, N. Collaert, 2016, SPIE Advanced Lithography.

Anticipation of nitrided oxides electrical thickness based on XPS measurement

M. Bidaud, J. Bienacel, D. Roy, 2004 .

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

Porosity and Pore Size Distributions of Porous Silicon Layers

K. Barla, K. Barla, G. Bomchil, 1987 .

Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

C. Merckling, N. Waldron, N. Collaert, 2016, 2016 IEEE Symposium on VLSI Technology.

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

L. Witters, N. Collaert, H. Bender, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

X-ray topographic characterization of porous silicon layers

K. Barla, J. Baruchel, K. Barla, 1984 .

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Low temperature deposition of 2D WS2 layers from WF6 and H2S precursors: impact of reducing agents.

S. De Gendt, S. Van Elshocht, H. Bender, 2015, Chemical communications.

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Plasma nitrided oxide films as a thin gate dielectric

K. Barla, A. Straboni, K. Barla, 1989 .

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Gerard Ghibaudo, C. Jahan, K. Barla, 1997 .

Quantitative Auger sputter depth profiling of very thin nitrided oxide

R. Pantel, K. Barla, A. Straboni, 1990 .

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Characteristics of SOI CMOS circuits made in n/n+/n oxidised porous silicon structures

K. Barla, A. Monroy, R. Herino, 1986 .

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

A Cost-Effective Low Power Platform for the 45-nm Technology Node

R. Ranica, O. Callen, M. Haond, 2006, 2006 International Electron Devices Meeting.

Determination of lattice parameter and elastic properties of porous silicon by X-ray diffraction

K. Barla, A. Freund, K. Barla, 1984 .

Boron diffusion effects from p+ polysilicon gate in thin thermal oxide and plasma nitrided oxide

K. Barla, A. Straboni, B. Piot, 1991, ESSDERC '91: 21st European Solid State Device Research Conference.

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

M. Badaroglu, L. Witters, D. Mocuta, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

The kinetics and mechanism of oxide layer formation from porous silicon formed on p‐Si substrates

K. Barla, K. Barla, G. Bomchil, 1987 .

Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform

N. Planes, N. Revil, B. Tavel, 2003, IEEE International Electron Devices Meeting 2003.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Microstructure of Porous silicon and its evolution with temperature

K. Barla, K. Barla, G. Bomchil, 1984 .

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

A. Vais, C. Merckling, N. Waldron, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).