C. P. Ravikumar

发表

Parallel r -dimensional placement on a vector minisupercomputer

C. P. Ravikumar, 1992 .

C. P. Ravikumar, Erik Jan Marinissen, Bashir M. Al-Hashimi, 2006, IEEE Design & Test of Computers.

An Architecture for CSP and Its Simulation

C. P. Ravikumar, Lalit M. Patnaik, 1987, ICPP.

Local at-speed scan enable generation for transition fault testing using low-cost testers

C. P. Ravikumar, Mark Mohammad Tehranipoor, Kenneth M. Butler, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving the diagnosability of digital circuits

C. P. Ravikumar, Manish Sharma, R. K. Patney, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Parallel Methods for Vlsi Layout Design

C. P. Ravikumar, Roman Trobec, R. Trobec, 1998, IEEE Concurrency.

An evolutionary scheme for cosynthesis of real-time systems

C. P. Ravikumar, S. Chakraverty, D. Roy Choudhuri, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

A genetic algorithm for assembling optical computers using faulty optical arrays

C. P. Ravikumar, Augustine R. Thomas, Abhay Gupta, 1996, Proceedings of 3rd International Conference on High Performance Computing (HiPC).

Parallel techniques for solving large scale travelling salesperson problems

C. P. Ravikumar, C. Ravikumar, 1992, Microprocess. Microsystems.

The hierarchical concurrent flow graph approach for modeling and analysis of design processes

C. P. Ravikumar, Vineet Sahula, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

On-chip signature checking for embedded memories

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1998, Proceedings Eleventh International Conference on VLSI Design.

Evaluating BIST architectures for low power

C. P. Ravikumar, N. Satya Prasad, C. Ravikumar, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

C. P. Ravikumar, R. Govindarajan, T. S. Rajesh Kumar, 2012, TECS.

Heuristic and neural algorithms for mapping tasks to a reconfigurable array

C. P. Ravikumar, Naresh Vedi, C. Ravikumar, 1995, Microprocess. Microprogramming.

Rapid synthesis of multi-chip systems

C. P. Ravikumar, Alice C. Parker, Dong-Hyun Heo, 1997, Proceedings Tenth International Conference on VLSI Design.

Message from the Program Chairs

C. P. Ravikumar, Takashi Nanya, Srimat, 2002, WORDS.

Testability-Driven Layout of Combinational Circuits

C. P. Ravikumar, Nikhil Sharma, 1998, VLSI Design.

Variation-Tolerant, Power-Safe Pattern Generation

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, IEEE Design & Test of Computers.

FREEDOM: statistical behavioral estimation of system energy and power

C. P. Ravikumar, Alice C. Parker, Suhrid A. Wadekar, 1998, Proceedings Eleventh International Conference on VLSI Design.

Estimation of power from module-level netlists

C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora, 1996, Proceedings of 9th International Conference on VLSI Design.

Built-in Self Test Based on Multiple On-Chip Signature Checking

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1999, J. Electron. Test..

A scheme for multiple on-chip signature checking for embedded SRAMs

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008

C. P. Ravikumar, Vojin G. Oklobdzija, Vijaykrishnan Narayanan, 2008, ISLPED.

Industrial Practices in Low-Power Robust Design

C. P. Ravikumar, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A framework for distributed and hierarchical design-for-test

C. P. Ravikumar, V. R. Devanathan, K. Kiran, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Adaptive Routing Based on Deadlock Recovery

C. P. Ravikumar, Nidhi Agrawal, 1998, Euro-Par.

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Kautz graphs as attractive logical topologies in multihop lightwave networks

C. P. Ravikumar, Tarun Rai, Varun Verma, 1997, Comput. Commun..

Genetic algorithm for mapping tasks onto a reconfigurable parallel processor

C. P. Ravikumar, A. K. Gupta, C. Ravikumar, 1995 .

Design issues in synthesis of reusable cores

C. P. Ravikumar, Rohit Sharma, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

An Euler path based technique for deadlock-free multicasting

C. P. Ravikumar, Nidhi Agrawal, 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).

HISCOAP: a hierarchical testability analysis tool

C. P. Ravikumar, Hemant Joshi, 1995, Proceedings of the 8th International Conference on VLSI Design.

Smart and Fault-Tolerant LED-Based Street Lamps

C. P. Ravikumar, 2016, J. Low Power Electron..

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

C. P. Ravikumar, R. Govindarajan, T. S. Rajesh Kumar, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A STAFAN-like functional testability measure for register-level circuits

C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal, 1995, Proceedings of the Fourth Asian Test Symposium.

Interval partition with bounded overlap

C. P. Ravikumar, 1992, Comput. Aided Des..

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2006, J. Low Power Electron..

Adaptive routing in k-ary n-cubes using incomplete diagnostic information

C. P. Ravikumar, C. S. Panda, 1997, Microprocess. Microsystems.

Solving Physical Design Problems on a Vector Machine

C. P. Ravikumar, 1992, The Fifth International Conference on VLSI Design.

Power-Aware System-Level DfT and Test Planning

Erik G. Larsson, C. P. Ravikumar, 2009 .

Static Verification of Test Vectors for IR Drop Failure

C. P. Ravikumar, Aman A. Kokrady, 2003, ICCAD 2003.

High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications

C. P. Ravikumar, 1999, Scalable Comput. Pract. Exp..

Parallel search-and-learn techniques and graph coloring

C. P. Ravikumar, R. Aggarwal, 1996, Knowl. Based Syst..

Efficient implementation of ADPCM codec

C. P. Ravikumar, Anil Sharma, C. Ravikumar, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Source-based delay-bounded multicasting in multimedia networks

C. P. Ravikumar, Rajneesh Bajpai, C. Ravikumar, 1998, Comput. Commun..

Simultaneous module selection and scheduling for power-constrained testing of core based systems

C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Star-Graph based multistage interconnection network for ATM switch fabric

C. P. Ravikumar, G. Manimaran, 1994, Proceedings of 1994 6th IEEE Symposium on Parallel and Distributed Processing.

A Hierarchical Genetic Algorithm for Hardware Software Co-Synthesis with a Stochastic Approach

C. P. Ravikumar, S. Chakraverty, D Roy Choudhuri, 2002 .

Genetic algorithms for scan path design

C. P. Ravikumar, Rajamani Rajarajan, 1996, Proceedings of 9th International Conference on VLSI Design.

Estimating crosstalk from VLSI layouts

C. P. Ravikumar, V. Sankara Subramanian, V. Subramanian, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis

C. P. Ravikumar, V. Saxena, C. Ravikumar, 1996, VLSI Design.

A functional-level testability measure for register-level circuits and its estimation

C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal, 1999, Microprocess. Microsystems.

Efficient delay test generation for modular circuits

C. P. Ravikumar, Parul Agarwal, Nidhi Agrawal, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

Simulated annealing for target-oriented partial scan

C. P. Ravikumar, H. Rasheed, 1994, Proceedings of 7th International Conference on VLSI Design.

Parallel placement on reduced array architecture

C. P. Ravikumar, Sarma Sastry, C. Ravikumar, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

Static Verification of Test Vectors for IR Drop Failure

C. P. Ravikumar, Aman Kokrady, 2003, ICCAD.

A self-checking signature scheme for checking backdoor security attacks in Internet

C. P. Ravikumar, Mohammed Fadle Abdulla, M. Abdulla, 2004, J. High Speed Networks.

Verilog modeling and simulation of a communication coprocessor for multicomputers

C. P. Ravikumar, A. Shyamprakash, 1995, Proceedings. 1995 IEEE International Verilog HDL Conference.

Design planning for single chip implementation of digital wireless mobile transceiver

C. P. Ravikumar, V. Sahula, 2000, 2000 IEEE International Conference on Personal Wireless Communications. Conference Proceedings (Cat. No.00TH8488).

Parallelization of symmetry detection algorithms on a network of workstations

C. P. Ravikumar, R. Parthiban, R. Kakarala, 1997, Microprocess. Microsystems.

A hardware accelerator for hierarchical VLSI routing

C. P. Ravikumar, Sarma Sastry, 1989, Integr..

A holistic parallel and hierarchical approach towards design-for-test

C. P. Ravikumar, Graham Hetherington, 2004, 2004 International Conferce on Test.

A polynomial-time algorithm for power constrained testing of core based systems

C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Distributed Fault Simulation Algorithms on Parallel Virtual Machine

C. P. Ravikumar, Vikas Jain, Anurag Dod, 2001, VLSI Design.

Design of Wavelength Division Multiplexed Networks for Delay-Bound Multicasting

C. P. Ravikumar, Prachi Jain, Meeta Sharma, 1999 .

Test Strategies for Low-Power Devices

C. P. Ravikumar, Xiaoqing Wen, Mokhtar Hirech, 2008, J. Low Power Electron..

Testing interconnects in a system chip

C. P. Ravikumar, S. Chopra, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Design of WDM Networks for Delay-Bound Multicasting

C. P. Ravikumar, Prachi Jain, Meeta Sharma, 1999, HiPC.

Optimal code and data layout in embedded systems

C. P. Ravikumar, R. Govindarajan, T. S. Rajesh Kumar, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

On Power-profiling and Pattern Generation for Power-safe Scan Tests

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Software power optimizations in an embedded system

C. P. Ravikumar, Vishal Dalal, C. Ravikumar, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Low-Power Hierarchical Scan Test for Multiple Clock Domains

C. P. Ravikumar, S. K. Nandy, Arasu T. Senthil, 2007, J. Low Power Electron..

Divide-and-conquer IDDQ testing for core-based system chips

C. P. Ravikumar, Rahul Kumar, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Incomplete Star Graph : An Economical Fault-tolerant Interconnection Network

C. P. Ravikumar, G. Manimaran, A. Kuchlous, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Efficient algorithms for delay-bounded minimum cost path problem in communication networks

C. P. Ravikumar, Girish Kumar, Nishit Narang, 1998, Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238).

The second Oxford workshop on CAD accelerators: a report

C. P. Ravikumar, 1990, SIGD.

Performance improvement of simulated annealing algorithms

C. P. Ravikumar, Lalit M. Patnaik, L. Patnaik, 1990, Computer systems science and engineering.

Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation pdf

C. P. Ravikumar, Vineet Sahula, Namita Sharma, 2013, ArXiv.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

C. P. Ravikumar, R. Govindarajan, T. S. Rajesh Kumar, 2007, 2007 Asia and South Pacific Design Automation Conference.

A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer

C. P. Ravikumar, S. K. Nandy, Arasu T. Senthil, 2005, IEEE International Conference on Test, 2005..

Adding an Easy "Search" Option in a Music Player Using a Capacitive Touch Interface

C. P. Ravikumar, Sanjeev Kumar, 2013, 2013 Texas Instruments India Educators' Conference.

Efficient implementation of multiple on-chip signature checking

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1997, Proceedings Tenth International Conference on VLSI Design.

Improvement of ASIC design processes

C. P. Ravikumar, D. Nagchoudhuri, Vineet Sahula, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Conference Reports

C. P. Ravikumar, Jari Nurmi, 2004, IEEE Design & Test of Computers.

Parallel circuit partitioning on a reduced array architecture

C. P. Ravikumar, Lalit M. Patnaik, S. Sastry, 1989 .

A scheme for multiple on-chip signature checking for embedded SRAMS

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 2000, J. Syst. Archit..

Parallel search-and-learn technique for solving large scale travelling-salesperson problems

C. P. Ravikumar, 1994, Knowl. Based Syst..

Synthesis of testable pipelined datapaths using genetic search

C. P. Ravikumar, V. Saxena, C. Ravikumar, 1996, Proceedings of 9th International Conference on VLSI Design.

Enhanced launch-off-capture transition fault testing

C. P. Ravikumar, Mark Mohammad Tehranipoor, Nisar Ahmed, 2005, IEEE International Conference on Test, 2005..

Two-way partitioning of shuffle-exchange and DeBruijn graphs

C. P. Ravikumar, A. Kuchlous, 1995 .

Leakage power estimation for deep submicron circuits in an ASIC design environment

C. P. Ravikumar, Rahul Kumar, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Synthesis of testable RTL designs

C. P. Ravikumar, Sumit Gupta, Akshay Jajoo, 1998, Proceedings Eleventh International Conference on VLSI Design.

Parallel Placement on Hypercube Architecture

C. P. Ravikumar, Sarma Sastry, 1989, ICPP.

Distributed delay constrained multicast path setup algorithm for high speed networks

C. P. Ravikumar, Suresh Chandra, Ramnik Bajaj, 1997, Proceedings Fourth International Conference on High-Performance Computing.

An evolutionary approach to system redesign

C. P. Ravikumar, Alice C. Parker, Dong-Hyun Heo, 1998, Proceedings Eleventh International Conference on VLSI Design.

At-speed transition fault testing with low speed scan enable

C. P. Ravikumar, Mark Mohammad Tehranipoor, James F. Plusquellic, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications

C. P. Ravikumar, Girish Kumar, Nishit Narang, 1999, HiPC.

SCOAP-based Testability Analysis from Hierarchical Netlists

C. P. Ravikumar, Hemant Joshi, 1998, VLSI Design.

VYUHA: A detailed router for multiple routing models

C. P. Ravikumar, Sarma Sastry, 1991, Integr..

Memory Architecture Exploration Framework for Cache Based Embedded SOC

C. P. Ravikumar, R. Govindarajan, T. S. Rajesh Kumar, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides

C. P. Ravikumar, Yervant Zorian, Laung-Terng Wang, 2007, 16th Asian Test Symposium (ATS 2007).

Hierarchical Delay Test Generation

C. P. Ravikumar, Nitin Agrawal, Parul Agarwal, 1997, J. Electron. Test..

Multiprocessor Architectures for Embedded Video Streaming Applications

C. P. Ravikumar, 2003 .

Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1998, J. Electron. Test..

Mutual testing based on wavelet transforms

C. P. Ravikumar, N. Kakkar, S. Chopra, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Fault-tolerant routing in multiply twisted cube topology

C. P. Ravikumar, Nidhi Agrawal, 1996, J. Syst. Archit..

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 2007 IEEE International Test Conference.

VDAT 2002 Call for Papers

C. P. Ravikumar, Rubin A. Parekhji, V. Shenoy, 2002 .

Solving VLSI physical design problems on a vector machine

C. P. Ravikumar, 1993, Comput. Aided Des..

Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security

C. P. Ravikumar, Ananya Ravikumar, 2018, J. Low Power Electron..

Collaborative DFT Practices Needed for Low-Cost Testing

C. P. Ravikumar, Srivaths Ravi, 2007 .

Faster fault simulation through distributed computing

C. P. Ravikumar, Vikas Jain, Anurag Dod, 1997, Proceedings Tenth International Conference on VLSI Design.

A graph-theoretic approach for register file based synthesis

C. P. Ravikumar, R. Aggarwal, C. Sharma, 1997, Proceedings Tenth International Conference on VLSI Design.

Proceedings of the 2014 international symposium on Low power electronics and design

C. P. Ravikumar, Vojin G. Oklobdzija, Vijaykrishnan Narayanan, 2006 .

Simulated Annealing for Target-Oriented Scan.

C. P. Ravikumar, H. Rasheed, 1994 .

A critical-path-aware partial gating approach for test power reduction

C. P. Ravikumar, Mark Mohammad Tehranipoor, Mohammed ElShoukry, 2007, TODE.

A novel BIST architecture with built-in self check

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1996, Proceedings of 9th International Conference on VLSI Design.

Multi-Core Architectures for Embedded Systems

C. P. Ravikumar, C. Ravikumar, 2018 .

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2008, J. Low Power Electron..

Fast, layout-aware validation of test-vectors for nanometer-related timing failures

C. P. Ravikumar, Aman Kokrady, C. Ravikumar, 2004, 17th International Conference on VLSI Design. Proceedings..

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 2007 IEEE International Test Conference.

VLSI implementation of a wormhole router using virtual channels

C. P. Ravikumar, A. S. Prakash, 1994, Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology'.

Deadlock-free wormhole routing algorithms for star graph topology

C. P. Ravikumar, Anand M. Goel, 1995 .

Hybrid testing schemes based on mutual and signature testing

C. P. Ravikumar, Anshul Kumar, Mohammed Fadle Abdulla, 1998, Proceedings Eleventh International Conference on VLSI Design.

Test Strategies for Low Power Devices

C. P. Ravikumar, Xiaoqing Wen, Mokhtar Hirech, 2008, 2008 Design, Automation and Test in Europe.

A fuzzy-logic based morse code entry system with a touch-pad interface for physically disabled persons

C. P. Ravikumar, Manikanta Dathi, 2016, 2016 IEEE Annual India Conference (INDICON).

Performance-driven design and redesign of high-speed local area networks

C. P. Ravikumar, Anubhav Mishra, Dilip R. Pandit, 1998, Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238).

A parallel search-and-learn technique for solving large scale TSP

C. P. Ravikumar, 1993, Proceedings of 1993 IEEE Conference on Tools with Al (TAI-93).

Wireless multicasting: design and performance analysis

C. P. Ravikumar, A. Mishra, 1999, 1999 IEEE International Conference on Personal Wireless Communications (Cat. No.99TH8366).

Hierarchical delay fault simulation

C. P. Ravikumar, Ajay Mittal, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Multiprocessor architectures for embedded system-on-chip applications

C. P. Ravikumar, C. Ravikumar, 2004, 17th International Conference on VLSI Design. Proceedings..

Application of Parallel and Distributed Data Mining in e-Commerce

C. P. Ravikumar, M M Sufyan Beg, 2000 .

A Stochastic Framework for Co-synthesis of Real-Time Systems

C. P. Ravikumar, S. Chakraverty, C. Ravikumar, 2000, LCTES.

Power-Aware System-Level Test Planning

Erik G. Larsson, C. P. Ravikumar, 2010 .

Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models

C. P. Ravikumar, Nitin Chandrachoodan, Aman Kokrady, 2008, 21st International Conference on VLSI Design (VLSID 2008).

SHARP: A shape recognition system and its parallel implementation

C. P. Ravikumar, Rajender Sethi, 1995, Microprocess. Microsystems.

Partial Gating Optimization for Power Reduction During Test Application

C. P. Ravikumar, Mark Mohammad Tehranipoor, Mohammed ElShoukry, 2005, 14th Asian Test Symposium (ATS'05).

Proceedings of the 2008 international symposium on Low Power Electronics & Design

C. P. Ravikumar, Vojin G. Oklobdzija, Vijaykrishnan Narayanan, 2008, ISLPED 2008.

Measuring the Quality of Web Search Results

C. P. Ravikumar, Mirza Mohd. Sufyan Beg, 2002, JCIS.

Design Technology Challenges in the Sub-100 Nanometer Era

C. P. Ravikumar, Vinod Menezes, V. Vishvanathan, 2006 .

Optimal Design of Delay-Bounded WDM Networks using a Genetic Algorithm

C. P. Ravikumar, Meeta Sharma, Prachi Jain, 2002 .