Ming-Tung Chang

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction

Shianling Wu, Xiaoqing Wen, Boryau Sheu, 2005, IEEE International Conference on Test, 2005..

Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax

Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

TSV redundancy: Architecture and design issues in 3D IC

TingTing Hwang, Ang-Chih Hsieh, Ming-Tung Chang, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Test clock domain optimization for peak power supply noise reduction during scan

Chien-Mo James Li, Jen-Yang Wen, Yu-Chuan Huang, 2011, 2011 IEEE International Test Conference.

BIST design optimization for large-scale embedded memory cores

Yao-Wen Chang, Chien-Mo James Li, Ming-Tung Chang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering

Ming-Tung Chang, Wei-Sheng Ding, Min-Hsiu Tsai, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing retention flip-flops in power-gated designs

Mango Chia-Tso Chao, Hao-Wen Hsu, Shi-Hao Chen, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise

Jen-Yang Wen, Ming-Tung Chang, Min-Hsiu Tsai, 2008, 2008 IEEE International Test Conference.

A method and apparatus for diagnosing failures in an integrated circuit using techniques of the type design-for-debug (DFD)

Hsin-Po Wang, Hao-Jan Chao, Shyh-Horng Lin, 2002 .