Yuang Zhang

An RBF neural network–based dynamic virtual network embedding algorithm

Hui Zhang, Xiangwei Zheng, Qingshui Xue, 2019, Concurr. Comput. Pract. Exp..

A survey of memory architecture for 3D chip multi-processors

Axel Jantsch, Zhonghai Lu, Feng Han, 2014, Microprocess. Microsystems.

Implementation of JPEG decoding based on AMBA-AHB multi-processor architecture: Implementation of JPEG decoding based on AMBA-AHB multi-processor architecture

Li Li, Lan Dong, Yuang Zhang, 2010 .

Performance and power consumption analysis of memory efficient 3D network-on-chip architecture

Xiao Yu, Li Li, Hongbing Pan, 2013, 2013 10th IEEE International Conference on Control and Automation (ICCA).

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links

Li Li, Feng Han, Kun Wang, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A scalable distributed memory architecture for Network on Chip

Lan Dong, Li Li, Minglun Gao, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Multi-Objective Virtual Network Embedding Algorithm Based on Global Resource Capacity

Zhen Li, Xiangwei Zheng, Qingshui Xue, 2017, 22017 IEEE International Conference on Computational Science and Engineering (CSE) and IEEE International Conference on Embedded and Ubiquitous Computing (EUC).

An Analysis Method for Subliminal Affective Priming Effect Based on CEEMDAN and MPE

Xiangwei Zheng, Yuang Zhang, Min Zhang, 2019, ChineseCSCW.

Fixed-time attitude control for spacecraft without unwinding

Bing Huang, Yong Guo, Yuang Zhang, 2017, 2017 International Conference on Mechanical, System and Control Engineering (ICMSC).

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC

Xiao Yu, Li Li, Hongbing Pan, 2013, 2013 10th IEEE International Conference on Control and Automation (ICCA).

Memory Architecture and Management in an NoC Platform

Axel Jantsch, Zhonghai Lu, Xiaowen Chen, 2012 .

Exploring stacked main memory architecture for 3D GPGPUs

Li Li, Axel Jantsch, Zhonghai Lu, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Towards hierarchical cluster based cache coherence for large-scale network-on-chip

Zhonghai Lu, Li Li, Minglun Gao, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips

Axel Jantsch, Zhonghai Lu, Yuxiang Fu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Multidomain Survivable Virtual Network Mapping Algorithm

Xiangwei Zheng, Yuang Zhang, Xian-cui Xiao, 2017, Secur. Commun. Networks.