Ondrej Novák

发表

Application dependent FPGA testing method using compressed deterministic test vectors

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

C. P. Ravikumar, Erik Jan Marinissen, Bashir M. Al-Hashimi, 2006, IEEE Design & Test of Computers.

Relocation of reconfigurable modules on Xilinx FPGA

Martin Rozkovec, Ondrej Novák, Tomas Drahonovsky, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Sequential Test Decompressors with Fast Tester Bits Wide-Spreading

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2017, J. Circuits Syst. Comput..

Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata

Ondrej Novák, O. Novák, 1999, EDCC.

Test pattern decompression in parallel scan chain architecture

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

An empirical model of UWB large-scale signal fading in neocortical research

Ondrej Novák, Richard B. Brown, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Sequential test decompressors with fast variable wide spreading

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017)

Ondrej Novák, Witold A. Pleskacz, Zoran Stamenkovic, 2018, Microelectron. Reliab..

Application Dependent FPGA Testing Method

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Reduction of the Transferred Test Data Amount

Ondrej Novák, 2011 .

A highly flexible reconfigurable system on a Xilinx FPGA

Martin Rozkovec, Ondrej Novák, Tomas Drahonovsky, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

Comparison of test pattern decompression techniques

Ondrej Novák, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Logic testing with test-per-clock pattern loading and improved diagnostic abilities

Ondrej Novák, Zdenek Plíva, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits

Ondrej Novák, Zdenek Plíva, Jirí Zahrádka, 2005, EDCC.

FPGA-based fault simulator

Ondrej Novák, Leos Kafka, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW

Ondrej Novák, Martin Stáva, 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

COMPAS — Advanced test compressor

Jiri Jenícek, Ondrej Novák, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Hw implementation of the backtrace algorithm with conflict-driven dynamic reconfiguration

Ondrej Novák, Martin Stáva, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

On test time reduction using pattern overlapping, broadcasting and on-chip decompression

Jiri Jenícek, Ondrej Novák, Martin Chloupek, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Advanced scan chain configuration method for broadcast decompressor architecture

Jiri Jenícek, Ondrej Novák, Martin Chloupek, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

Extended binary nonlinear codes and their application in testing and compression

Ondrej Novák, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Test vector overlapping based compression tool for narrow test access mechanism

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Test Pattern Compression Based on Pattern Overlapping

Jiri Jenícek, Ondrej Novák, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

On using deterministic test sets in BIST

Ondrej Novák, Jiri Nosek, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Test response compaction method with improved detection and diagnostic abilities

Ondrej Novák, Zdenek Plíva, 2018, Microelectron. Reliab..

Test pattern decompression using a scan chain

Ondrej Novák, Jiri Nosek, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Test-per-clock testing of the circuits with scan

Ondrej Novák, Jiri Nosek, 2001, Proceedings Seventh International On-Line Testing Workshop.

Test-data compression with low number of channels and short test time

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Test compression for circuits with multiple scan chains

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2015, 2015 16th Latin-American Test Symposium (LATS).

Structural test of programmed FPGA circuits

Martin Rozkovec, Ondrej Novák, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

Jiri Jenícek, Ondrej Novák, Zbynek Mader, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Test Decompressor Effectivity Improvement

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Formation and disruption of tonotopy in a large-scale model of the auditory cortex

Ondrej Novák, Josef Syka, Jakub Tomek, 2015, Journal of Computational Neuroscience.

An evaluation of the application dependent FPGA test method

Martin Rozkovec, Jiri Jenícek, Ondrej Novák, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage

Ondrej Novák, Jan Hlavicka, P. Golan, 1988, IEEE Trans. Computers.

Altered expression of maize PLASTOCHRON1 enhances biomass and seed yield by extending cell division duration

Ondrej Novák, Dirk Inzé, Veronique Storme, 2017, Nature Communications.