Jorge Echavarria

Probability-Based DSE of Approximated LUT-Based FPGA Designs

Jürgen Teich, Oliver Keszocze, Jorge Echavarria, 2022, 2022 IEEE 15th Dallas Circuit And System Conference (DCAS).

Modelo con enfoque logístico para diagnosticar la gestión de mantenimiento de una entidad productora de envases // Model with logistical approach to diagnose maintenance in a packaging producer company

Jesús Cabrera Gómez, Jorge Echavarria, E. Germán, 2020 .

IP-cores watermarking scheme at behavioral level using genetic algorithms

Claudia Feregrino Uribe, René Cumplido, Jorge Echavarria, 2021, Eng. Appl. Artif. Intell..

FSM merging and reduction for IP cores watermarking using Genetic Algorithms

René Cumplido, Miguel A. Salido, Jorge Echavarria, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*

Jürgen Teich, Muhammad Abdullah Hanif, Arnaud Virazel, 2021, 2021 IEEE European Test Symposium (ETS).

AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs

Jürgen Teich, Stefan Wildermann, Jorge Echavarria, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs

Jürgen Teich, Stefan Wildermann, Andreas Becher, 2016, 2016 International Conference on Field-Programmable Technology (FPT).