Gopinath Mahale

REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores

S. K. Nandy, Ranjani Narayan, Gopinath Mahale, 2016, IEEE Transactions on Parallel and Distributed Systems.

Hardware architecture of bi-cubic convolution interpolation for real-time image scaling

S. Bhattacharya, S. K. Nandy, Gopinath Mahale, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices

Sehwan Lee, Gopinath Mahale, Pramod Udupa, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

IKW: Inter-Kernel Weights for Power Efficient Edge Computing

Gopinath Mahale, Sehwan Lee, Pramod Udupa, 2020, IEEE Access.

Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures

Gopinath Mahale, Sehwan Lee, Pramod Udupa, 2020, ISCAS.

On the modeling of error functions as high dimensional landscapes for weight initialization in learning networks

Julius, Gopinath Mahale, T. Sumana, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks

S. K. Nandy, Ranjani Narayan, Gopinath Mahale, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Hardware Solution for Real-Time Face Recognition

S. Bhattacharya, S. K. Nandy, Ranjani Narayan, 2015, 2015 28th International Conference on VLSI Design.