Shigetoshi Nakatake

Self-reforming routing for stochastic search in VLSI interconnection layout

Yoji Kajitani, Yukiko Kubo, Yasuhiro Takashima, 2000, ASP-DAC '00.

Multi-level placement with circuit schema based clustering in analog IC layouts

Yoji Kajitani, Yasuhiro Takashima, Shigetoshi Nakatake, 2004 .

Placement algorithm for rectilinear core cells by multilayered parametric BSG

Yoji Kajitani, Shigetoshi Nakatake, Keishi Sakanushi, 2004 .

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

Sequence-Pair Based Compaction under Equi-Length Constraint

Shigetoshi Nakatake, Keiji Kida, Takehiko Matsuo, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A new sparse design framework for broadband power amplifier behavioral modeling and digital predistortion

Mingyu Li, Chuan Li, Yu Zhang, 2014 .

Abstraction and optimization of consistent floorplanning with pillar block constraints

Yoji Kajitani, Ning Fu, Yasuhiro Takashima, 2004 .

Module placement on BSG-structure and IC layout applications

Yoji Kajitani, Hiroshi Murata, Kunihiro Fujiyoshi, 1996, ICCAD 1996.

Structured Placement with Topological Regularity Evaluation

Shigetoshi Nakatake, 2007, 2007 Asia and South Pacific Design Automation Conference.

A consistent local congestion avoiding strategy for iterative improvement of cross point assignment

Shigetoshi Nakatake, Changwen Zhuang, Yoji Kajitani, 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.

Iterative Generation of Steiner Trees by Flip for Optimum Interconnection Layout

Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani, 1998 .

Floorplanning consistent with partial-clustering on the sequence-pair

Shigetoshi Nakatake, Xiaoke Zhu, Yoji Kajitani, 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.