Yifan He

发表

Machine Learning for Electronic Design Automation: A Survey

Yu Wang, Xuefei Ning, Bei Yu, 2021, ACM Trans. Design Autom. Electr. Syst..

Machine Learning for Electronic Design Automation: A Survey

Kai Zhong, Jialong Liu, Huazhong Yang, 2021, ACM Trans. Design Autom. Electr. Syst..

An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance

Siyuan Qiu, Hailong Jiao, Yifan He, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration

Yifan He, Henk Corporaal, Zoran Zivkovic, 2008, ACIVS.

Real-time implementations of Hough Transform on SIMD architecture

Yifan He, Henk Corporaal, Zoran Zivkovic, 2008, 2008 Second ACM/IEEE International Conference on Distributed Smart Cameras.

Efficient communication support in predictable heterogeneous MPSoC designs for streaming applications

Sander Stuijk, Yifan He, Henk Corporaal, 2013, J. Syst. Archit..

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture

Meilin Liu, Yongpan Liu, Xueqing Li, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

7.3 A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference

Yongpan Liu, Xueqing Li, Jinshan Yue, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

Huazhong Yang, Yongpan Liu, Jinshan Yue, 2023, IEEE Transactions on Circuits and Systems II: Express Briefs.

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs

Yifan He, Henk Corporaal, Akash Kumar, 2013, 2013 International Symposium on Rapid System Prototyping (RSP).

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse

Meng-Fan Chang, Xueqing Li, Huazhong Yang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution

Huazhong Yang, Yongpan Liu, Jinshan Yue, 2023, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

Nan Sun, Huazhong Yang, Yongpan Liu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array

Huazhong Yang, Yongpan Liu, Dejun Mu, 2023, IEEE Transactions on Circuits and Systems - II - Express Briefs.

Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems

Huazhong Yang, Yongpan Liu, Jinshan Yue, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations

Yongpan Liu, Jinshan Yue, Wenyu Sun, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

Huazhong Yang, Meilin Liu, Yongpan Liu, 2022, IEEE Journal of Solid-State Circuits.

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture

Yongpan Liu, Jinshan Yue, Yifan He, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

RQNoC

Yifan He, Ioannis Sourdis, Gerard K. Rauwerda, 2016, ACM Trans. Embed. Comput. Syst..

A configurable SIMD architecture with explicit datapath for intelligent learning

Yifan He, Henk Corporaal, Maurice Peemen, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design

Yongpan Liu, Jinshan Yue, Yifan He, 2024, IEEE Transactions on Circuits and Systems II: Express Briefs.

Scheduling for register file energy minimization in explicit datapath architectures

Yifan He, Henk Corporaal, Bart Mesman, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).