M. Ieong

发表

Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs

H.-S.P. Wong, Y. Taur, M. Ieong, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Process induced stress for CMOS performance improvement

J.J. Kim, M. Ieong, S. Fang, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

Anna W. Topol, D.J. Frank, G.M. Cohen, 2002, Digest. International Electron Devices Meeting,.

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

J. Sudijono, H. Utomo, M. Ieong, 2007, 2007 IEEE Symposium on VLSI Technology.

Investigation of FinFET Devices for 32nm Technologies and Beyond

M. Ieong, L. Chang, W. Haensch, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/HfO/sub 2/)

R. Jammy, M. Ieong, T. Ning, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

J. Sudijono, D. Shum, J.J. Kim, 2006, 2006 International Electron Devices Meeting.

Soft error rate scaling for emerging SOI technology options

K. Bernstein, H.-S.P. Wong, P. Oldiges, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)

M. Ieong, W. Haensch, J. Kedzierski, 2003, IEEE International Electron Devices Meeting 2003.

Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates

Y.H. Kim, M. Ieong, T. Kanarsky, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

P. Oldiges, K. Maitra, V. Narayanan, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS

C. Sheraw, B. Haran, C.-C. Yang, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

D. Mocuta, S. Narasimha, A. Mocuta, 2002, Digest. International Electron Devices Meeting,.

Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks

Y.H. Kim, V. Narayanan, R. Carruthers, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Dual work function metal gate CMOS using CVD metal electrodes

V. Narayanan, R. Jammy, C. Wann, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs

P. Oldiges, V. Narayanan, M. Steen, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Fabrication, device design and mobility enhancement of germanium channel MOSFETs

X. Wang, M. Ieong, H. Shang, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

On the integration of CMOS with hybrid crystal orientations

K. Bernstein, P. Oldiges, M. Ieong, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations

J. Patel, J. Sleight, M. Ieong, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Dual stress liner enhancement in hybrid orientation technology

M. Ieong, T. Kanarsky, D. Chidambarrao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Strained ultrahigh performance fully depleted nMOSFETs with f/sub t/ of 330 GHz and sub-30-nm gate lengths

J. Sleight, M. Ieong, Z. Ren, 2006, IEEE Electron Device Letters.

Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond

M. Ieong, O. Dokumaci, W. Haensch, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

J. Patel, Anna W. Topol, A. Kumar, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon

R. Dennard, M. Ieong, D. F. Heidel, 2000 .

Channel design and mobility enhancement in strained germanium buried channel MOSFETs

M. Ieong, H. Shang, X. Wang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

M. Ieong, Z. Ren, O. Dokumaci, 2005, 2005 IEEE International SOI Conference Proceedings.