Y. Watanabe

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

T. Ohsawa, T. Higashi, A. Nitayama, 2006, 2006 International Electron Devices Meeting.

Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

Shigeyoshi Watanabe, Yukihito Oowaki, Daisaburo Takashima, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

Word-line architecture for highly reliable 64-Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1992 .

A 33ns 64Mb DRAM

Shigeyoshi Watanabe, Fumio Horiguchi, Yukihito Oowaki, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.