Hubert Kaeslin

发表

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

Wolfgang Fichtner, Felix Bürgin, Flavio Carbognani, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 1994 .

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

Wolfgang Fichtner, Flavio Carbognani, Hubert Kaeslin, 2008 .

Variable delay ripple carry adder with carry chain interrupt detection

Andreas Peter Burg, Wolfgang Fichtner, Hubert Kaeslin, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

VINCI: VLSI implementation of the new secret-key block cipher IDEA

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications

Wolfgang Fichtner, Felix Bürgin, Flavio Carbognani, 2005, PATMOS.

Towards Edge-Aware Spatio-Temporal Filtering in Real-Time

Luca Benini, Hubert Kaeslin, Aljosa Smolic, 2018, IEEE Transactions on Image Processing.

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2013, VLSI-SoC.

Sparsity-based real-time audio restoration

Andreas Peter Burg, Hubert Kaeslin, Norbert Felber, 2012, Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing.

A 2.7-µW/MHz Transmission-Gate-Based 16-bit Multiplier for Digital Hearing Aids

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2005 .

A 0.67-mm/sup 2/ 45-/spl mu/W DSP VLSI implementation of an adaptive directional microphone for hearing aids

Herbert Koch, Wolfgang Fichtner, Felix Bürgin, 2005, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005..

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing

Richard G. Baraniuk, Arian Maleki, Andreas Peter Burg, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Speech coding for energy-efficient digital signal processing

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

High-speed compressed sensing reconstruction on FPGA using OMP and AMP

Hubert Kaeslin, Lin Bai, Patrick Maechler, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Architectural design and realization of a single-chip Viterbi decoder

Hubert Kaeslin, Carlo Tommasini, Marc Biver, 1989, Integr..

Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

On the GALS design methodology of ETH Zurich

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2003 .

Compressive sensing for WiFi-based passive bistatic radar

Hubert Kaeslin, Norbert Felber, Patrick Maechler, 2012, 2012 Proceedings of the 20th European Signal Processing Conference (EUSIPCO).

Regular VLSI architectures for multiplication modulo (2/sup n/+1)

Hubert Kaeslin, A. Curiger, H. Bonnenberg, 1991 .

Modelling Hardware with VHDL

Hubert Kaeslin, 2008 .

A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication

Wolfgang Fichtner, Felix Bürgin, Flavio Carbognani, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Automatic multiview synthesis — Prototype demo

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2015, 2015 Visual Communications and Image Processing (VCIP).

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2016, IEEE Transactions on Circuits and Systems for Video Technology.

A hardware architecture for surface splatting

Timo Aila, Tim Weyrich, Markus H. Gross, 2007, ACM Trans. Graph..

Digital Integrated Circuit Design: Clocking of Synchronous Circuits

Hubert Kaeslin, 2008 .

Hardware implementations of the SHA-3 candidates Shabal and CubeHash

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Top-Down Digital VLSI Design: From Architectures to Gate-Level Circuits and FPGAs

Hubert Kaeslin, H. Kaeslin, 2014 .

29% Power Saving through Semi-Custom Standard Cell Re-Design in a Front-End for Hearing Aids

Wolfgang Fichtner, Flavio Carbognani, Hubert Kaeslin, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX

Hubert Kaeslin, 1988, it Inf. Technol..

MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping

Aljoscha Smolic, Hubert Kaeslin, Michael Schaffner, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

In-place updating of path metrics in Viterbi decoders

Hubert Kaeslin, M. Biver, C. Tommasini, 1989 .

A systematic approach to the extraction of diphone elements from natural speech

Hubert Kaeslin, 1986, IEEE Trans. Acoust. Speech Signal Process..

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis

Wolfgang Fichtner, Hubert Kaeslin, Frank K. Gürkaynak, 2002, CHES.

Self-timed ring for globally-asynchronous locally-synchronous systems

Wolfgang Fichtner, Hubert Kaeslin, Frank K. Gürkaynak, 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

High-speed VLSI workpiece position measurement using normalized 2Dcorrelation

Hubert Kaeslin, Norbert Felber, Fritz M. Rothacher, 1994, Electronic Imaging.

A hardware architecture for surface splatting

Timo Aila, Tim Weyrich, Markus Gross, 2007, SIGGRAPH 2007.

Digital Integrated Circuit Design: References

Hubert Kaeslin, 2008 .

Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications

Aljoscha Smolic, Markus H. Gross, Hubert Kaeslin, 2013, IEEE Transactions on Circuits and Systems for Video Technology.

Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers

Hubert Kaeslin, Norbert Felber, Frank K. Gürkaynak, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Acquisition of Asynchronous Data

Hubert Kaeslin, 2008 .

Digital Integrated Circuit Design: VLSI Economics and Project Management

Hubert Kaeslin, 2008 .

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Digital Integrated Circuit Design: Physical Design

Hubert Kaeslin, 2008 .

Hardware-efficient random sampling of fourier-sparse signals

Andreas Peter Burg, Hubert Kaeslin, Norbert Felber, 2012, 2012 IEEE International Symposium on Circuits and Systems.

SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC

Luca Benini, Hubert Kaeslin, Michael Gautschi, 2014, 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors.

Application of Graph Theory to Topology Generation for Logic Gates

Hubert Kaeslin, 1988, WG.

VLSI Designer's Checklist

Hubert Kaeslin, 2008 .

Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication

Hubert Kaeslin, H. Kaeslin, 2008 .

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

Wolfgang Fichtner, Felix Bürgin, Flavio Carbognani, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits

Hubert Kaeslin, Robert Rogenmoser, Tobias Blickle, 1996, PPSN.

The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Circuits

Hubert Kaeslin, Norbert Felber, Robert Rogenmoser, 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

A new and secure selftest scheme for block cipher implementations

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 1993, Proceedings ETC 93 Third European Test Conference.

A 0.67-mm2 45-W DSP VLSI implementation of an adaptive directional microphone for hearing aids

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2005 .

From Algorithms to Architectures

Hubert Kaeslin, 2008 .

The Case for Synchronous Design

Hubert Kaeslin, 2008 .

42% power savings through glitch-reducing clocking strategy in a hearing aid application

Wolfgang Fichtner, Felix Bürgin, Flavio Carbognani, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Digital Integrated Circuit Design: Functional Verification

Hubert Kaeslin, 2008 .

Digital Integrated Circuit Design: Finite State Machines

Hubert Kaeslin, 2008 .

Waveform coding for low-power digital filtering of speech data

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2003, IEEE Trans. Signal Process..

VINCI: Secure test of a VLSI high-speed encryption system

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 1993, Proceedings of IEEE International Test Conference - (ITC).

Semiconductor Technology and the Energy Efficiency of ICT

Hubert Kaeslin, 2015, ICT Innovations for Sustainability.

Live demonstration: Real-time audio restoration using sparse signal recovery

Andreas Peter Burg, Hubert Kaeslin, Norbert Felber, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 2 Gb/s balanced AES crypto-chip implementation

Andreas Peter Burg, Wolfgang Fichtner, Hubert Kaeslin, 2004, GLSVLSI '04.

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2006, Electron. Notes Theor. Comput. Sci..

Digital Integrated Circuit Design: Design Verification

Hubert Kaeslin, 2008 .

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2002, ASYNC.

Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications

Wolfgang Fichtner, Felix Bürgin, Flavio Carbognani, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A real-time 720p feature extraction core based on Semantic Kernels Binarized

Hubert Kaeslin, Lukas Cavigelli, Michael Schaffner, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Design and Verification of a Stack Processor Virtual Component

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2001, IEEE Micro.

Automatic multiview synthesis — Towards a mobile system on a chip

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2015, 2015 Visual Communications and Image Processing (VCIP).

An approximate computing technique for reducing the complexity of a direct-solver for sparse linear systems in real-time video processing

Luca Benini, Aljoscha Smolic, Hubert Kaeslin, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Systematische Gewinnung und Verkettung von Diphonelementen für die Synthese deutscher Standardsprache

Hubert Kaeslin, 1985 .

Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications

Aljoscha Smolic, Markus H. Gross, Andreas Peter Burg, 2012, IEEE Transactions on Circuits and Systems for Video Technology.

VLSI – tailored Architectures for Multiplication modulo (2n + 1)

Hubert Kaeslin, Andreas Curiger, Heinz Bonnenberg, 1990, ESSCIRC '90: Sixteenth European Solid-State Circuits Conference.

GALS at ETH Zurich: success or failure?

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space

Hubert Kaeslin, 1986, Speech Commun..

Digital Integrated Circuit Design: Gate- and Transistor-Level Design

Hubert Kaeslin, 2008 .

Digital Integrated Circuit Design: Introduction to Microelectronics

Hubert Kaeslin, H. Kaeslin, 2008 .

Digital Integrated Circuit Design: Outlook

Hubert Kaeslin, 2008 .

Hardware Evaluation of Estream Candidates

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2006 .

Cell-Based Multilevel Carry-Increment Adders with Minimal AT- and PT-Products

Hubert Kaeslin, Reto Zimmermann, 1996 .

Design flow for a 3-million transistor GALS test chip

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, 2002 .

Lessons Learned from Designing a 65 nm ASIC for Evaluating Third Round SHA-3 Candidates

Kris Gaj, Hubert Kaeslin, Frank K. Gürkaynak, 2012 .

Is there hope for GALS in the future ?

Wolfgang Fichtner, Hubert Kaeslin, Norbert Felber, .

Globally-asynchronous locally-synchronous architectures for VLSI systems

Hubert Kaeslin, Frank Kesel, librum adprehende, 2008 .