Jaspal Singh Shah

Low-Power Soft-Error-Robust Embedded SRAM

Jaspal Singh Shah, 2013 .

A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

Jaspal Singh Shah, David Nairn, Manoj Sachdev, 2015, IEEE Transactions on Nuclear Science.

A 64-bit, 2.4 GHz adder with SE detection capabilities employing time redundancy

Jaspal Singh Shah, Manoj Sachdev, Pierce Chuang, 2009 .

An Energy-Efficient Offset-Cancelling Sense Amplifier

Jaspal Singh Shah, David Nairn, Manoj Sachdev, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design of Soft Error Robust High Speed 64-bit Logarithmic Adder

Jaspal Singh Shah, 2009 .

Radiation hardened pulsed-latches in 65-nm CMOS

Jaspal Singh Shah, Manoj Sachdev, 2016, 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm

Jaspal Singh Shah, David Nairn, Manoj Sachdev, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Design of a novel high-performance reduced clock-swing pre-discharge flip-flop

Jaspal Singh Shah, Manoj Sachdev, Pierce Chuang, 2009 .