C.-W. Wu

发表

C-testable systolic array design for LZ data compression

S.-A. Hwang, C.-W. Wu, 1997 .

Test generation for combinational iterative logic arrays

C.-W. Wu, 1989 .

Realisation of pipelined mesh algorithms on hypercubes

C.-W. Wu, K.-J. Lin, 1992 .

Determination of cost coefficients of a priority-based water allocation linear programming model – a network flow approach

Frederick N.-F. Chou, C.-W. Wu, F. Chou, 2013 .

An adaptive code rate EDAC scheme for 16-bit random access memory

C.-Y. Chen, C.-W. Wu, 2010, DATE 2010.

Graph-based power-constrained test scheduling for SOC

C.-P. Su, C.-W. Wu, 2002 .

Cellular automata for efficient parallel fault simulation

Yih-Lang Li, C.-W. Wu, C. Wu, 1993 .

ADAPTABLE SPLINE ELEMENT FOR MEMBRANE VIBRATION ANALYSIS

C.-W. Wu, W. H. Chen, 1996 .

Spatial-temporal fractionally spaced decision-feedback equalisation for fading channels with dispersive interference

C.-W. Wu, S.-C. Lin, 2011, IET Commun..

A test controller for system-on-chip designs with test wrappers

Jin-Fu Li, H.-J. Huang, C.-P. Su, 2001 .

An Efficient Multi-Mode Multiplier Supporting AES and Fundamental Operations of Public-Key Crypto-Systems

C.-H. Wang, C.-W. Wu, C.-L. Chuang, 2009 .

Is automotive electronics creating new opportunities for semiconductor

C.-W. Wu, J.-J. Tang, 2010 .

Built-in self-forming, built-in self-test, and built-in self-repair for RRAM yield improvement

C.-H. Lin, C.-Y. Chen, C.-W. Wu, 2011 .

Economic analysis of built-in self-test for logic and memory cores

C.-W. Wu, J.-M. Lu, 1999 .

PMBC: a programmable BIST compiler for memory cores

C.-W. Wu, K.-J. Lin, 1999 .

Design of efficient totally self-checking checkers for m-out-of-n code

C.-W. Wu, W.-F. Chang, 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

Totally self-checking checkers for m-out-of-n code with lower hardware complexity

C.-W. Wu, W.-F. Chang, 1993 .

Comments on theoretical foundation of “EM Drive”

C.-W. Wu, 2018 .