D. K. Pradhan

发表

Fault-tolerant multiprocessor and VLSI-based system communication architectures

D. K. Pradhan, 1986 .

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

H. Rahaman, D. K. Pradhan, A. K. Singh, 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.

A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization

D. K. Pradhan, S. Banerjee, J. Mathew, 2010, 2010 International Symposium on Electronic System Design.

REACT: a synthesis and evaluation tool for fault-tolerant multiprocessor architectures

J. A. Clark, D. K. Pradhan, J. Clark, 1993, Annual Reliability and Maintainability Symposium 1993 Proceedings.

8. Recent Advances in Verification, Equivalence Checking

D. K. Pradhan, 2003 .

Comment on "Nonplanar VLSI arrays with high fault-tolerance capabilities

D. K. Pradhan, I. Koren, 1989 .

Correction to 'The De Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI'

M. R. Samatham, D. K. Pradhan, 1991 .

A single cached copy data coherence scheme for multiprocessor systems

A. D. Singh, A. Mendelson, D. K. Pradhan, 1989, CARN.

Critical computer applications will growexplosively inthenext decade, demanding systems thatarereliable andavailable. Faulttolerance provides thetools tobuild suchsystems.

D. K. Pradhan, 1980 .

De-Bruijn Graph Based Energy Efficient Routing in Multi-layered Architecture for Wireless Sensor Networks

Vishram Mishra, J. Mathew, Anas Abu Taleb, 2009 .

Multiple Bit Error Detection and Correction in GF Arithmetic Circuits

J. Mathew, D. K. Pradhan, P. Mahesh, 2010, 2010 International Symposium on Electronic System Design.