Sharada Jha

Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults

Sharada Jha, S. Jha, 2013 .

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects

Masud H. Chowdhury, Abinash Roy, Sharada Jha, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

A Cube-Aware Compaction Method for Scan ATPG

Sudhakar M. Reddy, Kameshwar Chandrasekar, Ramesh Sharma, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.