M. Sakao

A 0.13 /spl mu/m full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation

H. Kawamoto, I. Naritake, T. Iizuka, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

H. Kitamura, H. Kawamoto, T. Yamamoto, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Y. Takai, S. Nakazawa, Y. Kobayashi, 2000, IEEE Journal of Solid-State Circuits.

Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time

K. Yoshida, T. Sakoh, M. Sakao, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme

Y. Takai, M. Fujita, H. Ohkubo, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

M. Sakao, T. Ishijima, K. Terada, 1990 .

A 30 ns 64 Mb DRAM with built-in self-test and repair function

N. Kasai, M. Takada, A. Tanabe, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

T. Sakoh, M. Sakao, M. Hamada, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

M. Sakao, T. Ishijima, K. Terada, 1987, 1987 International Electron Devices Meeting.