Vinay Vashishtha

发表

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node

Lawrence T. Clark, Vinay Vashishtha, L. Clark, 2021, Microelectron. J..

Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit

Ankita Dosi, Lawrence T. Clark, Vinay Vashishtha, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

ASAP7: A finFET-Based Framework for Academic VLSI Design at the 7 nm Node

Lawrence T. Clark, Vinay Vashishtha, 2018 .

Vinay Vashishtha, 2014 .

High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness

Srivatsan Chellappa, Lawrence T. Clark, Chandarasekaran Ramamurthy, 2015, IEEE Transactions on Nuclear Science.

Design with sub-10 nm FinFET technologies

Lawrence T. Clark, Vinay Vashishtha, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

Robust 7-nm SRAM design on a predictive PDK

Lawrence T. Clark, Vinay Vashishtha, Manoj Vangala, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation

Srivatsan Chellappa, Lawrence T. Clark, Chandarasekaran Ramamurthy, 2015, Sixteenth International Symposium on Quality Electronic Design.

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper

Lawrence T. Clark, Vinay Vashishtha, Manoj Vangala, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Power consumption improvement with residue code for fault tolerance on SRAM FPGA

Vinay Vashishtha, Amiel Frederic, Ea Thomas, 2011, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP).

Delay and power tradeoffs for static and dynamic register files

Lawrence T. Clark, Vinay Vashishtha, Aditya Gujja, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A FinFET-Based Framework for VLSI Design at the 7 nm Node

Lawrence T. Clark, Vinay Vashishtha, 2019 .

Predictive Process Design Kits for the 7 nm and 5 nm Technology Nodes

Vinay Vashishtha, 2019 .

A soft-error hardened process portable embedded microprocessor

Srivatsan Chellappa, Lawrence T. Clark, Vinay Vashishtha, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning

Ankita Dosi, Lawrence T. Clark, Chandarasekaran Ramamurthy, 2017, Advanced Lithography.

ASAP7: A 7-nm finFET predictive process design kit

Saurabh Sinha, Brian Cline, Greg Yeric, 2016, Microelectron. J..

Architectural and Micro-Architectural Techniques for Software Controlled Microprocessor Soft-Error Mitigation

Srivatsan Chellappa, Lawrence T. Clark, Vinay Vashishtha, 2015, 2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit

Lawrence T. Clark, David M. Harris, Vinay Vashishtha, 2017, 2017 IEEE International Conference on Microelectronic Systems Education (MSE).

A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

Lawrence T. Clark, Vinay Vashishtha, Aditya Gujja, 2016, IEEE Transactions on Nuclear Science.