A. Rubio

发表

Error probability in synchronous digital circuits due to power supply noise

F. Martorell, M. Pons, A. Rubio, 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic

A. Rubio, D. Mateo, 1998 .

Temperature sensors and measurements to test analogue circuits: questions and answers

F. Reverter, X. Perpina, M. Vellvehi, 2016, 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).

memFET: From gate dielectric breakdown to system reconfigurability

A. Rubio, A. Crespo-Yepes, J. Martin-Martinez, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Impact of FinFET Technology Introduction in the 3T1D-DRAM Memory Cell

A. Rubio, C. G. Almudever, E. Amat, 2013, IEEE Transactions on Device and Materials Reliability.

Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

A. Rubio, C. G. Almudever, E. Amat, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

A. Rubio, F. Moll, D. Mateo, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Testability aspects of folded source-coupled logic

A. Rubio, J. L. Gonzalez, 1997 .

A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits

A. Rubio, D. Andrade, A. Calomarde, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Active charge collection strategy for radiation environment at device level

A. Rubio, F. Moll, F. Gamiz, 2016, 2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Analysis of cross-talk effects on logic cell delays in CMOS integrated circuits

A. Rubio, F. Moll, Etienne Sicard, 1991, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems.

On the Variability-aware Design of Memristor-based Logic Circuits

A. Rubio, M. Escudero, I. Vourkas, 2018, 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO).

SRAM lifetime improvement by using adaptive proactive reconfiguration

A. Rubio, E. Amat, P. Pouyan, 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.

Highlevel Spectral-based analysis ofPower Consumption inDSPssystems

A. Rubio, D. Mateo, A. Calomarde, 2006 .

Improving board and system test: a proposal to integrate boundary scan and I/sub DDQ/

A. Rubio, D. Reed, J. Doege, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations

A. Rubio, Carmen G. Almudever, 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.

Strain relevance on the improvement of the 3T1D cell performance

A. Rubio, C. G. Almudever, E. Amat, 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.

Low switching noise CMOS circuit design strategy based on regular self-timed structures

A. Rubio, J. L. Gonzalez, 1998, 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268).

Variability Mitigation Mechanisms in Scaled 3T1D-DRAM Memories to 22 nm and Beyond

A. Rubio, C. G. Almudever, E. Amat, 2013, IEEE Transactions on Device and Materials Reliability.

Fault tolerant structures for nanoscale gates

F. Martorell, A. Rubio, S.D. Cotofana, 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).

Power supply noise and logic error probability

M. Pons, A. Rubio, F. Moll, 2007, 2007 18th European Conference on Circuit Theory and Design.

Variability impact on on-chip memory data paths

A. Rubio, R. Canal, A. Calomarde, 2014, 2014 5th European Workshop on CMOS Variability (VARI).

Manufacturability Issues of Redundant Nanogates

F. Martorell, A. Rubio, S.D. Cotofana, 2007, 2007 International Semiconductor Conference.

Analysis of crosstalk interference in CMOS integrated circuits

A. Rubio, Etienne Sicard, A. Rubio, 1992 .

Defect and fault tolerant cell architecture for feasible nanoelectronic designs

A. Rubio, F. Martorell, A. Rubio, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Adaptive Fault-Tolerant Architecture for Unreliable Technologies With Heterogeneous Variability

A. Rubio, N. Aymerich, S. D. Cotofana, 2012, IEEE Transactions on Nanotechnology.

A single event transient hardening circuit design technique based on strengthening

A. Rubio, F. Moll, E. Amat, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Ground bounce modelling for digital gigascale integrated circuits

X. Aragones, M. Pons, A. Rubio, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Off-chip Iddq monitor with standard test interface

A. Rubio, J. Pedros, 1995 .

I/sub DDQ/ testing of oscillating bridging faults in CMOS combinational circuits

E. Sicard, A. Rubio, M. Roca, 1993 .

Test pattern generation for logic crosstalk faults in VLSI circuits

A. Rubio, J. A. Sainz, K. Kinoshita, 1991 .

Selftesting CMOS operational amplifier

A. Rubio, M. Roca, 1992 .