A. Vaidyanath

Design and analysis of a TB/sec memory system

Ken Chang, W.T. Beyene, C. Yuan, 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

Characterization and hardware correlation of multi-gigahertz parallel bus with transmit pre-emphasis equalization

W.T. Beyene, C. Yuan, A. Vaidyanath, 2004, Electrical Performance of Electronic Packaging - 2004.

Challenges in extending single-ended graphics memory data rates

Dan Oh, A. Vaidyanath, S. Mukherjee, 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

Optimizing the timing center for high-speed parallel buses

Dan Oh, Woopoung Kim, C. Madden, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

A tri-modal 20Gbps/link differential/DDR3/GDDR5 memory interface

A. Amirkhany, C. Yuan, K. Kaviani, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Simultaneous switching noise: influence of plane-plane and plane-signal trace coupling

A. Vaidyanath, B. Thoroddsen, A.C. Cangellaris, 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.