Adil Bhanji

Generation and use of statistical timing macro-models considering slew and load variability

Jin Hu, Vladimir Zolotov, Debjit Sinha, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Hierarchical Transistor and Gate-Level Statistical Timing Flow for Microprocessor Designs

Sachin Gupta, Chandu Visweswariah, Debjit Sinha, 2009 .

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

Debjit Sinha, Adil Bhanji, Chaobo Li, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).