D. Henry

发表

Curved microdisplay, from optical design to mechanical study: impact on form-factor and light efficiency in visual systems

S. Charrière, P. L. Joly, B. Simon, 2020, Photonics Europe.

3D integration process flow for set-top box application: Description of technology and electrical results

A. Astier, P. Chausse, S. Cheramy, 2009, 2009 European Microelectronics and Packaging Conference.

Low electrical resistance silicon through vias: technology and characterization

C. Brunet-Manquat, N. Sillon, D. Henry, 2006, 56th Electronic Components and Technology Conference 2006.

Survey of High-Temperature Reliability of Power Electronics Packaging Components

L. Mendizabal, D. Henry, R. Khazaka, 2015, IEEE Transactions on Power Electronics.

Chapter 5 – The Neutral Beam Test Facility Cryopumping Operation: Preliminary Analysis and Design of the Cryogenic System

R. S. Hemsworth, J. J. Cordier, M. Dremel, 2005 .

3D integration technology for hybrid pixel detectors designed for particle physics and imaging experiments

M. Campbell, D. Henry, C. Chantre, 2012, 2012 4th Electronic System-Integration Technology Conference.

Experimental and modelling thermal study of a 3D-stacked silicon based LEDs array concept

D. Henry, P. Rueda, A. Gasse, 2017, 2017 23rd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

Silicon Through Vias for System-on-Wafer (SoW): Technology and SiO2 Insulation Layer Characterization

C. Brunet-Manquat, N. Sillon, D. Henry, 2006, 2006 1st Electronic Systemintegration Technology Conference.

3D integration design & technology for hybrid pixel detectors used for particle physics and imaging experiments

M. Campbell, D. Henry, C. Chantre, 2012, 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG).

3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

G. Cibrario, R. Franiatte, A. Farcy, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Facilitating Ultrathin Wafer Handling for TSV Processing

M. Zussy, J. Brun, N. Sillon, 2008, 2008 10th Electronics Packaging Technology Conference.

Process and RF modelling of TSV last approach for 3D RF interposer

R. Anciant, A. Farcy, P. Chausse, 2011, 2011 IEEE International Interconnect Technology Conference.

Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

R. Anciant, N. Sillon, D. Henry, 2009, 2009 11th Electronics Packaging Technology Conference.

Thermal management: A key point for the integration in solid state lighting systems

D. Henry, N. Lhermet, A. Gasse, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

Development and characterisation of high electrical performances TSV for 3D applications

A. Farcy, P. Chausse, G. Garnier, 2009, 2009 11th Electronics Packaging Technology Conference.

New trends in wafer level packaging

J. Brun, S. Cheramy, N. Sillon, 2009, 2009 IEEE International Interconnect Technology Conference.

Effects of stress in polysilicon VIA - first TSV technology

N. Sillon, D. Henry, N. Bresson, 2010, 2010 12th Electronics Packaging Technology Conference.

Through silicon vias technology for CMOS image sensors packaging

X. Baillin, C. Brunet-Manquat, N. Sillon, 2008, 2008 58th Electronic Components and Technology Conference.

Wafer level packaging technology development for CMOS image sensors using Through Silicon Vias

C. Brunet-Manquat, N. Sillon, D. Henry, 2008, 2008 2nd Electronics System-Integration Technology Conference.

Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon

X. Baillin, N. Sillon, D. Henry, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

TSV as an alternative to wire bonding for a wireless industrial product: another step towards 3D integration

A. Farcy, P. Ancey, G. Garnier, 2010, 3rd Electronics System Integration Technology Conference ESTC.

3D Integration : a technological toolbox

L. Clavelier, N. Sillon, D. Henry, 2008, 2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference.

Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results

R. Anciant, P. Chausse, N. Hotellier, 2008, 2008 10th Electronics Packaging Technology Conference.

Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs

L. Di Cioccio, N. Sillon, D. Henry, 2008, 2008 IEEE International Electron Devices Meeting.