A. Dandache

A polynomial division pipelined architecture for CRC error detecting codes

B. Lepley, F. Monteiro, A. Dandache, 2001, ICM 2001 Proceedings. The 13th International Conference on Microelectronics..

Fast parallel architecture for syndrome convolutional decoder

A. Dandache, A. M'sir, F. Monteiro, 2002, The 14th International Conference on Microelectronics,.

A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division

A. Dandache, A. M'sir, F. Monteiro, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).