Chee Houe Khong

Design and analysis of 3D stacked optoelectronics on optical printed circuit boards

Jing Li, John H. Lau, Jing Zhang, 2008, SPIE OPTO.

Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs)

Srinivasa Rao Vempati, Chee Houe Khong, Ser Choong Chong, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects

John H. Lau, Ying Ying Lim, K. Y. Au, 2009, 2009 59th Electronic Components and Technology Conference.

Sub-modeling technique for thermo-mechanical simulation of solder microbumps assembly in 3D chip stacking

Dim-Lee Kwong, V. Kripesh, Aibin Yu, 2009, 2009 11th Electronics Packaging Technology Conference.

A novel method to predict die shift during compression molding in embedded wafer level package

Dim-Lee Kwong, Srinivasa Rao Vempati, Kripesh Vaidyanathan, 2009, 2009 59th Electronic Components and Technology Conference.