Yuta Kimi

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, Fifteenth International Symposium on Quality Electronic Design.

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Time-Dependent Degradation in Device Characteristics and Countermeasures by Design

Masahiko Yoshimoto, Masanori Hashimoto, Shuhei Tanakamaru, 2018, VLSI Design and Test for Systems Dependability.

An accurate soft error propagation analysis technique considering temporal masking disablement

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015 .

Design of SRAM Resilient Against Dynamic Voltage Variations

Yohei Nakata, Koji Nii, Masahiko Yoshimoto, 2019 .

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Electron..

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, IEICE Trans. Electron..

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, ARCS Workshops.