Stanislaw J. Piestrak

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Design of Self-Testing Checkers for Borden Codes

Stanislaw J. Piestrak, 1996, IEEE Trans. Computers.

Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'

Stanislaw J. Piestrak, 2002, IEEE Trans. Computers.

Stanislaw J. Piestrak, S. Piestrak, S. E L F-C H E C K I N G C I R C U I T S, 2004 .

On the design of self-testing checkers for modified Berger codes

Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos, 2001, Proceedings Seventh International On-Line Testing Workshop.

Characterizing laser-induced pulses in ICs: methodology and results

Fabrice Monteiro, Abbas Dandache, Stanislaw J. Piestrak, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Exploiting residue number system for power-efficient digital signal processing in embedded processors

Aviral Shrivastava, Stanislaw J. Piestrak, Krzysztof S. Berezowski, 2009, CASES '09.

Design of Fault-Secure Multipliers-Accumulators and {FIR} Filters Protected Using Residue Codes

Stanislaw J. Piestrak, Piotr Patronik, S. Piestrak, 2014, Euromicro Symposium on Digital Systems Design.

Fast and energy-efficient constant-coefficient FIR filters using residue number system

Aviral Shrivastava, Stanislaw J. Piestrak, Krzysztof S. Berezowski, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters

Stanislaw J. Piestrak, 1998, J. Electron. Test..

The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes

Stanislaw J. Piestrak, S. Piestrak, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Implementation and evaluation of configuration scrubbing on CGRAs: A case study

Hannu Tenhunen, Juha Plosila, Stanislaw J. Piestrak, 2013, 2013 International Symposium on System on Chip (SoC).

Design of an RNS reverse converter for a new five-moduli special set

Aviral Shrivastava, Stanislaw J. Piestrak, Krzysztof S. Berezowski, 2012, GLSVLSI '12.

VLSI implementation and complexity comparison of residue generators modulo 3

Olivier Sentieys, Stanislaw J. Piestrak, Fabrice Pedron, 1998, 9th European Signal Processing Conference (EUSIPCO 1998).

Design of the coarse-grained reconfigurable architecture DART with on-line error detection

Olivier Sentieys, Sébastien Pillement, Stanislaw J. Piestrak, 2014, Microprocess. Microsystems.

Design of residue generators and multioperand modular adders using carry-save adders

Stanislaw J. Piestrak, S. Piestrak, 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs

Hannu Tenhunen, Juha Plosila, Stanislaw J. Piestrak, 2013, 2013 Euromicro Conference on Digital System Design.

Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set $$\{2^{k}, 2^{n} - 1, 2^{n} + 1, 2^{n+1} - 1, 2^{n-1} - 1\}$${2k,2n-1,2n+1,2n+1-1,2n-1-1} (n Even)

Stanislaw J. Piestrak, Piotr Patronik, 2018, Circuits Syst. Signal Process..

Design of Reverse Converters for General RNS Moduli Sets $\{ 2^{k}, 2^{n}-1, 2^{n}+1, 2^{n+1}-1 \}$ and $\{ 2^{k}, 2^{n}-1, 2^{n}+1, 2^{n-1}-1 \}$ ($n$ even)

Stanislaw J. Piestrak, Piotr Patronik, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels

Stanislaw J. Piestrak, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Error recovery technique for coarse-grained reconfigurable architectures

Olivier Sentieys, Sébastien Pillement, Stanislaw J. Piestrak, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Design of cost-efficient multipliers modulo 2a−1

Stanislaw J. Piestrak, S. Piestrak, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Design of Fast Self-Testing Checkers for a Class of Berger Codes

Stanislaw J. Piestrak, S. Piestrak, 1987, IEEE Transactions on Computers.

Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes

Stanislaw J. Piestrak, 1990, IEEE Trans. Computers.

Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs

Sébastien Pillement, Stanislaw J. Piestrak, B. Chagun Basha, 2014, ARC.

Feasibility study of designing TSC sequential circuits with 100% fault coverage

Stanislaw J. Piestrak, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Membership test logic for delay-insensitive codes

Stanislaw J. Piestrak, 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Design of minimal-level PLA self-testing checkers for m-out-of-n codes

Stanislaw J. Piestrak, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor

Sébastien Pillement, Stanislaw J. Piestrak, Hung-Manh Pham, 2013, IEEE Transactions on Computers.

Private reliability environments for efficient fault-tolerance in CGRAs

Hannu Tenhunen, Juha Plosila, Stanislaw J. Piestrak, 2014, Des. Autom. Embed. Syst..

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication"

Olivier Sentieys, Sébastien Pillement, Stanislaw J. Piestrak, 2010, IEEE Communications Letters.

A note on RNS architectures for the implementation of the diagonal function

Stanislaw J. Piestrak, 2015, Inf. Process. Lett..

Fault-tolerant implementation of direct FIR filters protected using residue codes

Stanislaw J. Piestrak, Piotr Patronik, 2015, 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

Design of multi-residue generators using shared logic

Stanislaw J. Piestrak, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

General design of area-efficient PLA self-testing checkers for 1-out-of-n codes

Stanislaw J. Piestrak, 1994 .

Designing fault-secure parallel encoders for systematic linear error correcting codes

Fabrice Monteiro, Abbas Dandache, Stanislaw J. Piestrak, 2003, IEEE Trans. Reliab..

Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits

Stanislaw J. Piestrak, Jerzy W. Greblicki, 1999, EDCC.

Design of residue generators with CLA/compressor trees and multi-bit EAC

Stanislaw J. Piestrak, Piotr Patronik, 2017, 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS).

Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes

Stanislaw J. Piestrak, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Design of a self-testing checker for Borden code

Stanislaw J. Piestrak, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Design of self-testing checkers for unidirectional error detecting codes

Stanislaw J. Piestrak, 1995, Scientific papers of the Institute of Technical Cybernetics of the Technical University of Wroclaw.

Design of TSC code-disjoint inverter-free PLA's for separable unordered codes

Stanislaw J. Piestrak, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels

Stanislaw J. Piestrak, Piotr Patronik, 2018, J. Signal Process. Syst..

Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes

Stanislaw J. Piestrak, 1991, Fault-Tolerant Computing Systems.

Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem

Stanislaw J. Piestrak, S. Piestrak, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Modeling of transients caused by a laser attack on smart cards

Fabrice Monteiro, Abbas Dandache, Stanislaw J. Piestrak, 2005, 11th IEEE International On-Line Testing Symposium.

Architecture of efficient RNS-based digital signal processor with very low-level pipelining

Stanislaw J. Piestrak, Krzysztof S. Berezowski, 2008 .

Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication

Olivier Sentieys, Sébastien Pillement, Stanislaw J. Piestrak, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders

Stanislaw J. Piestrak, 1994, IEEE Trans. Computers.

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes

Fabrice Monteiro, Abbas Dandache, Stanislaw J. Piestrak, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks

Stanislaw J. Piestrak, 1993, IEEE Trans. Computers.

Design of Reverse Converters for the New RNS Moduli Set $\{2^{n}+1,2^{n}-1,2^{n},2^{n-1}+1\}$ ($n$ odd)

Stanislaw J. Piestrak, Piotr Patronik, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design of a fault-tolerant coarse-grained

Olivier Sentieys, Sébastien Pillement, Stanislaw J. Piestrak, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Design of parallel fault-secure encoders for systematic cyclic block transmission codes

Fabrice Monteiro, Abbas Dandache, Stanislaw J. Piestrak, 2009, Microelectron. J..

Fault-aware configurable logic block for reliable reconfigurable FPGAs

Sébastien Pillement, Stanislaw J. Piestrak, B. Chagun Basha, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of fault-secure encoders for a class of systematic error correcting codes

Fabrice Monteiro, Abbas Dandache, Stanislaw J. Piestrak, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes

Stanislaw J. Piestrak, Piotr Patronik, S. Piestrak, 2014, 2014 17th Euromicro Conference on Digital System Design.

The Study of Monotonic Core Functions and Their Use to Build RNS Number Comparators

Stanislaw J. Piestrak, Nikolay I. Chervyakov, Mikhail Babenko, 2021 .

Design of fast self-testing checkers for m-out-of-2m and m-out-of-(2m ± 1) codes

Stanislaw J. Piestrak, 1993 .

Design of residue multipliers-accumulators using periodicity

Stanislaw J. Piestrak, Krzysztof S. Berezowski, 2008 .

Design of squarers modulo A with low-level pipelining

Stanislaw J. Piestrak, 2002 .