Marc Renaudin

发表

Gilles Sicard, Emmanuel Allier, Julien Goulier, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

AsyncRFID: fully asynchronous contactless systems, providing high data rates, low power and dynamic adaptation

Edith Beigné, Marc Renaudin, D. Caucheteux, 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

A 100dB dynamic range CMOS image sensor with global shutter

Gilles Sicard, Marc Renaudin, Estelle Labonne, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor

Marc Renaudin, Pascal Vivet, Frédéric Robin, 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2009, 2009 27th IEEE VLSI Test Symposium.

From Hardware Processes to Asynchronous Circuits via Petri Nets: an Application to Arbiter Design

Alex Yakovlev, Marc Renaudin, 2004 .

Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net

Laurent Fesquet, Marc Renaudin, Anh Vu Dihn Duc, 2002, IWLS.

Implementing Asynchronous Circuits on LUT Based FPGAs

Laurent Fesquet, Marc Renaudin, Jean-Baptiste Rigaud, 2002, FPL.

Comparing transient-fault effects on synchronous and on asynchronous circuits

Gilles Sicard, Ricardo Reis, Rodrigo Possamai Bastos, 2009, 2009 15th IEEE International On-Line Testing Symposium.

A Novel Asynchronous e-FPGA Architecture for Security Applications

Sylvain Guilley, Jean-Luc Danger, Laurent Fesquet, 2007, 2007 International Conference on Field-Programmable Technology.

The ARESA Project: Facilitating Research, Development and Commercialization of WSNs

Fabrice Valois, Andrzej Duda, Martin Heusse, 2007, 2007 4th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks.

Computationally efficient adaptive rate sampling and filtering

Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, 2007, 2007 15th European Signal Processing Conference.

A new analytical approach of the impact of jitter on continuous time delta sigma converters

Julien Goulier, Eric André, Marc Renaudin, 2007, 2007 IFIP International Conference on Very Large Scale Integration.

Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools

Alexandre Yakovlev, Marc Renaudin, Pascal Vivet, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Improving DPA and DFA resistance of circuits using asynchronous logic

Marc Renaudin, G. F. Bouesse, Y. Monnet, 2004 .

Programmable/Stoppable Oscillator Based on Self-Timed Rings

Laurent Fesquet, Marc Renaudin, Eslam Yahya, 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

Asynchronous circuits sensitivity to fault injection

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Marc Renaudin, Radu Mateescu, Hubert Garavel, 2018, 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

A programmable logic architecture for prototyping clockless circuits

Laurent Fesquet, Marc Renaudin, 2005, International Conference on Field Programmable Logic and Applications, 2005..

On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits

Gilles Sicard, Marc Renaudin, Aurélien Buhrig, 2006, J. Low Power Electron..

Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm

Marc Renaudin, Eslam Yahya, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications

Gilles Sicard, Marc Renaudin, Sylvain Clerc, 2009, ISLPED.

Improved process and its corresponding architecture for securing parallel operations of plural arithmetic units especially in image processing

Gilles Privat, Marc Renaudin, Patricia Planet, 1994 .

Real-time spike detection in EEG signals using the wavelet transform and a dedicated digital signal processor card

Marc Renaudin, Didier Clarençon, Patrick Gourmelon, 1996, Journal of Neuroscience Methods.

Low Power Asynchronous Processors

Laurent Fesquet, Marc Renaudin, João Leonardo Fragoso, 2004 .

Hardening techniques against transient faults for asynchronous circuits

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2005, 11th IEEE International On-Line Testing Symposium.

High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators

Laurent Fesquet, Marc Renaudin, Benoit Miscopein, 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.

A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling

Marc Renaudin, Pascal Vivet, Sylvain Miermont, 2007, PATMOS.

Adaptive rate filtering a computationally efficient signal processing approach

Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, 2014, Signal Process..

10 - Un réseau cellulaire VLSI fonctionnellement asynchrone pour le filtrage morphologique d'images

Gilles Privat, Marc Renaudin, F. Robin, 1997 .

Analyse du comportement des circuits asynchrones en présence de fautes

Regis Leveugle, Marc Renaudin, Y. Monnet, 2005 .

Asynchrnous Architecture for Sensor Network Nodes

Dominique Barthel, Marc Renaudin, Aurélien Buhrig, 2005, Med-Hoc-Net.

Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2006, IEEE Transactions on Computers.

Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders

Gilles Sicard, Marc Renaudin, João Leonardo Fragoso, 2003, PATMOS.

A current shaping methodology for lowering em disturbances in asynchronous circuits

Gilles Sicard, Marc Renaudin, Dhanistha Panyasak, 2004, Microelectron. J..

An asynchronous NOC architecture providing low latency service and its multi-level design framework

Fabien Clermidy, Edith Beigné, Marc Renaudin, 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

A new analytical approach of the impact of jitter on continuous time delta sigma converters

Julien Goulier, Eric André, Marc Renaudin, 2007, VLSI-SoC.

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems

Laurent Fesquet, Marc Renaudin, Jean-Baptiste Rigaud, 2001, VLSI-SOC.

Dynamic Voltage Scheduling for Real Time Asynchronous Systems

Laurent Fesquet, Marc Renaudin, Mohammed Es Salhiene, 2002, PATMOS.

Evaluating transient-fault effects on traditional C-element's implementations

Gilles Sicard, Ricardo Reis, Rodrigo Possamai Bastos, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Asynchronous FIR filters: towards a new digital processing chain

E. Allier, Marc Renaudin, F. Aeschlimann, 2004 .

Automatic generation of 1-of-M QDI asynchronous adders

Gilles Sicard, Marc Renaudin, João Leonardo Fragoso, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation

Yehea I. Ismail, Laurent Fesquet, Marc Renaudin, 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.

State-holding in Look-Up Tables: application to asynchronous logic

Laurent Fesquet, Marc Renaudin, M. Steiner, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Networks on Chip

Marc Renaudin, Piet Wambacq, Wido Kruijtzer, 2003, Springer US.

Physical Design of FPGA Interconnect to Prevent Information Leakage

Sylvain Guilley, Jean-Luc Danger, Laurent Fesquet, 2008, ARC.

Low-power systems on chips (SOCs)

Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés, 2001, DATE '01.

DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

Marc Renaudin, Fabien Germain, G. Fraidy Bouesse, 2005, Design, Automation and Test in Europe.

Clockless Design Performance Monitoring for Nanometer Technologies

Robin Wilson, Marc Renaudin, Sylvain Engels, 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling

Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, 2009, EURASIP J. Adv. Signal Process..

Adaptive Rate Filtering Fora Signal Driven Sampling Scheme

Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

A design framework for asynchronous/synchronous circuits based on CHP to HDL translation

Marc Renaudin, Pascal Vivet, Frédéric Robin, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Asynchronous Systems on Programmable Logic

Laurent Fesquet, Marc Renaudin, Jerome Quartana, 2005, ReCoSoC.

Evaluation architecturale VLSI de systèmes standard de codage ďimages

Gilles Privat, Marc Renaudin, 1991 .

TAST Profiler and Low Energy Asynchronous Design Methodology

Gilles Sicard, Kamel Slimani, Marc Renaudin, 2004, PATMOS.

High-level modeling and design of asynchronous arbiters for on-chip communication systems

Laurent Fesquet, Marc Renaudin, Jean-Baptiste Rigaud, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

The Gabor transform as a modulated filter bank system

Michel Poize, Marc Renaudin, Patrick Venier, 1993 .

ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems

Marc Renaudin, 2010, PATMOS.

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips

Laurent Fesquet, Marc Renaudin, Jerome Quartana, 2005, International Conference on Field Programmable Logic and Applications, 2005..

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback pdf

Sylvain Guilley, Jean-Luc Danger, Laurent Fesquet, 2011, ArXiv.

Asynchronous circuits transient faults sensitivity evaluation

Régis Leveugle, Marc Renaudin, Yannick Monnet, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Low-Power Asynchronous A/D Conversion

Gilles Sicard, Laurent Fesquet, Emmanuel Allier, 2002, PATMOS.

Motion estimation VLSI architecture for image coding

Gilles Privat, Marc Renaudin, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping

Laurent Fesquet, Marc Renaudin, Jerome Quartana, 2005, VLSI-SoC.

Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective

Gilles Privat, Marc Renaudin, Frédéric Robin, 1997, Int. J. Pattern Recognit. Artif. Intell..

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2010, 2010 15th IEEE European Test Symposium.

Watershed parallel algorithm for asynchronous processors array

Marc Renaudin, Franck Mamalet, Bruno Galilée, 2002, Proceedings. IEEE International Conference on Multimedia and Expo.

Asynchronous circuits and systems

Marc Renaudin, 2000 .

Spectral analysis of a signal driven sampling scheme

Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, 2006, 2006 14th European Signal Processing Conference.

Case Study of a Fault Attack on Asynchronous DES Crypto-Processors

Christophe Clavier, Régis Leveugle, Marc Renaudin, 2006, FDTC.

QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis

Marc Renaudin, Eslam Yahya, 2006, PATMOS.

The design of fast asynchronous adder structures and their implementation using DCVS logic

Bachar El Hassan, Marc Renaudin, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals

Gilles Sicard, Marc Renaudin, G. Fraidy Bouesse, 2005, VLSI-SoC.

AHMOSE: Towards a Circuit Level Solution for Process Variability

Marc Renaudin, Eslam Yahya, 2008 .

Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms

Gilles Privat, Marc Renaudin, Patricia Planet, 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

La technologie asynchrone au service de la réduction d’énergie dans les systèmes embarqués

Laurent Fesquet, Marc Renaudin, Mohammed Es Salhiene, 2004, Ann. des Télécommunications.

Asynchronous FIR filters: towards a new digital processing chain

Laurent Fesquet, Emmanuel Allier, Marc Renaudin, 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

Self timed division and square-root extraction

Bachar El Hassan, Marc Renaudin, Alain Guyot, 1996, Proceedings of 9th International Conference on VLSI Design.

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits

Laurent Fesquet, Marc Renaudin, Bertrand Folco, 2005, VLSI-SoC.

A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI

Robin Wilson, Marc Renaudin, Sylvain Engels, 2018, J. Low Power Electron..

An approach to the introduction of formal validation in an asynchronous circuit design flow

Dominique Borrione, Marc Renaudin, Jean-Baptiste Rigaud, 2003, 36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the.

An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform

Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin, 2008, J. Electr. Comput. Eng..

A general time domain approach for the design of perfect reconstruction modulated filter banks

Michel Poize, Marc Renaudin, Patrick Venier, 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Statistic Implementation of QDI Asynchronous Primitives

Gilles Sicard, Philippe Maurine, Marc Renaudin, 2003, PATMOS.

A Method to Design Compact Dual-rail Asynchronous Primitives

Philippe Maurine, Michel Robert, Marc Renaudin, 2005, PATMOS.

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

Régis Leveugle, Jessy Clédière, Paolo Maistri, 2011, Journal of Cryptology.

Security evaluation of dual rail logic against DPA attacks

Philippe Maurine, Michel Robert, Marc Renaudin, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Tiempo Asynchronous Circuits System Verilog Modeling Language

Marc Renaudin, Alain Fonkoua, 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

A Methodology for estimating energy consumption of QDI asynchronous circuits

Kamel Slimani, Gilles Sicard, Marc Renaudin, 2004 .

High security smartcards

Marc Renaudin, Fabien Germain, Laurent Sourgen, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A new asynchronous pipeline scheme: application to the design of a self-timed ring divider

Marc Renaudin, Alain Guyot, B. E. Hassan, 1996 .

Parallel Asynchronous Watershed Algorithm-Architecture

Marc Renaudin, Franck Mamalet, Bruno Galilée, 2007, IEEE Transactions on Parallel and Distributed Systems.

Fast algorithm for lapped nonorthogonal transform: application to the image Gabor transform

Michel Poize, Marc Renaudin, Patrick Venier, 1992, Other Conferences.

SMILE: A scalable microcontroller library element

A. K. Betts, Marc Renaudin, Ivo Bolsens, 1993, Microprocess. Microprogramming.

Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies

Gilles Sicard, Ricardo Reis, Rodrigo Possamai Bastos, 2010, Microelectron. Reliab..

Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays

Marc Renaudin, Eslam Yahya, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Asynchronous design: fault robustness and security characteristics

Marc Renaudin, Yannick Monnet, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Asynchronous SRT dividers: the real cost

Bachar El Hassan, Marc Renaudin, Alain Guyot, 1996, Proceedings ED&TC European Design and Test Conference.

Functionally asynchronous array processor for morphological filtering of greyscale images

Gilles Privat, Marc Renaudin, N. Van Den Bossche, 1996 .

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

A new class of asynchronous A/D converters based on time quantization

Gilles Sicard, Laurent Fesquet, Emmanuel Allier, 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

Constrained Asynchronous Ring Structures for Robust Digital Oscillators

Laurent Fesquet, Marc Renaudin, Benoit Miscopein, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Practical evaluation of fault countermeasures on asynchronous DES crypto processor

Régis Leveugle, Marc Renaudin, Pascal Moitrel, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Gilles Sicard, Marc Renaudin, Sylvain Clerc, 2011, TODE.

Asynchronous AES Crypto-Processor including Secured and Optimized Blocks

Marc Renaudin, Ghislain Bouesse, F. Germain, 2004 .

Estimation rapide du couple énergie/délai des circuits asynchrones QDI

Gilles Sicard, Marc Renaudin, J. Fragoso, 2007, Tech. Sci. Informatiques.