Daesik Moon

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Jae-Joon Song, Kyung-Soo Kim, Jongmin Kim, 2018, 2018 IEEE Symposium on VLSI Circuits.

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Junha Lee, Jung-Hwan Choi, Joon-Young Park, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Jongmin Kim, Jung-Hwan Choi, Joon-Young Park, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

Dongkeon Lee, Dukha Park, Byongwook Na, 2020, IEEE Journal of Solid-State Circuits.

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Hyoung-Joo Kim, Kiwon Lee, Joon-Young Park, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).