Cheol Kim

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Behaviors and Performance Evaluation of a Lightweight Piezo-Composite Curved Actuator

Nam Seo Goo, Young-Doo Kwon, Kwang Joon Yoon, 2001 .