Su-Yeon Doo

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Hyun-Soo Park, Hyuk-Jun Kwon, Jong-Ho Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Hyoung-Joo Kim, Jong-Ho Lee, Jun-Young Park, 2015, IEEE Journal of Solid-State Circuits.

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Hyun-Soo Park, Hyuk-Jun Kwon, Kyungbae Park, 2019, IEEE Journal of Solid-State Circuits.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Young-Hyun Jun, Dong-Min Kim, Young-Sik Kim, 2010, 2010 Symposium on VLSI Circuits.

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Hyoung-Joo Kim, Kiwon Lee, Joon-Young Park, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).