S. Teehan

Enhanced power factor of Indium co-doped ZnO:Al thin films deposited by RF sputtering for high temperature thermoelectrics

H. Efstathiadis, P. Haldar, S. Teehan, 2011 .

First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications

D. Edelstein, R. Johnson, J. Slaughter, 2021, International Electron Devices Meeting.

Temperature dependent thermal conductivity of Si/SiC amorphous multilayer films

H. Efstathiadis, T. Borca-Tasciuc, M. Mazumder, 2010 .

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Thermoelectric power factor enhancement of AZO/In-AZO quantum well multilayer structures as compared to bulk films

H. Efstathiadis, P. Haldar, S. Teehan, 2012 .

Thermoelectric Performance of ZnO:Al/ZnO:(Al,In) Quantum Well Multilayer Structures as a Function of Indium Composition and Band-Gap Offset at High Operating Temperatures

H. Efstathiadis, P. Haldar, S. Teehan, 2012, Journal of Electronic Materials.

Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules

S. Skordas, D. Mcherron, K. Hosokawa, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization

M. Rasch, V. Narayanan, R. Johnson, 2022, 2022 International Electron Devices Meeting (IEDM).