G. Neuendorf

Hierarchical architecture for fast CMOS SRAMs

D. Schmitt-Landsiedel, G. Neuendorf, B. Hoppe, 1989, Proceedings. VLSI and Computer Peripherals. COMPEURO 89.

Memory hierarchically structured from memory cell

Doris Schmitt-Landsiedel, G. Neuendorf, Hans-Joerg Dr Ing Pfleiderer, 1990 .

Polynomial delay models for optimisation-based transistor sizing in digital CMOS VLSI circuits

Doris Schmitt-Landsiedel, G. Neuendorf, Veronika Eisele, 1989 .

Automatic transistor sizing in high performance CMOS logic circuits

D. Schmitt-Landsiedel, G. Neuendorf, B. Hoppe, 1989, Proceedings. VLSI and Computer Peripherals. COMPEURO 89.

Pipelined architecture for fast CMOS buffer RAMs

G. Neuendorf, J. Winnerl, Bernhard Hoppe, 1990 .

Use of a cmos static memory array as a technology test vehicle

G. Neuendorf, J. Winnerl, Doris Dr Schmitt-Landsiedel, 1992 .

Pipelined 16k Buffer RAM with 300MHz Operating Frequency

D. Schmitt-Landsiedel, G. Neuendorf, B. Hoppe, 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.