Yasufumi Sakai

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

Eiji Yoshida, Hiroshi Yamazaki, Toshihiko Mori, 2014, IEEE Journal of Solid-State Circuits.

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

Tetsuro Tamura, Hiroshi Yamazaki, Kazuaki Oishi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Dropout and DropConnect for Reliable Neuromorphic Inference Under Communication Constraints in Network Connectivity

Gert Cauwenberghs, Siddharth Joshi, Bruno U. Pedroni, 2019, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design

Naoki Hamada, Teruo Ishihara, Yukito Tsunoda, 2019, GECCO.

DropOut and DropConnect for Reliable Neuromorphic Inference under Energy and Bandwidth Constraints in Network Connectivity

Gert Cauwenberghs, Siddharth Joshi, Bruno U. Pedroni, 2019, 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

A High-Speed Neural Architecture Search Considering the Number of Weights

Yasufumi Sakai, Fuyuka Yamada, Satoki Tsuji, 2021, KI.

Efficient and Large Scale Pre-training Techniques for Japanese Natural Language Processing

Akihiko Kasagi, Akihiro Tabuchi, Tsuguchika Tabaru, 2021, 2021 Ninth International Symposium on Computing and Networking (CANDAR).