Tomokazu Higuchi

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 0.12mm2 5Gbps receiver with a level shifting equalizer and a cumulative-histogram-based adaptation engine

Takuji Yamamoto, Hirotaka Tamura, Yasumoto Tomita, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

Hiroki Miyaoka, Atsushi Matsuda, Hirohito Higashi, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

Yoshiyasu Doi, Hirotaka Tamura, Masaya Kibune, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Clinical evaluation of assistive robotic arm

Takenobu Inoue, Jun Yamaguchi, Tsuyoshi Nakayama, 2012 .