B.J. Sheu

Automatic layout generation for mixed analog-digital VLSI neural chips

D.J. Chen, B.J. Sheu, 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Analog VLSI design of cellular neural networks with annealing agility

Wai-Chi Fang, B.J. Sheu, S.H. Bang, 1994, Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94).

Mr. Semiconductor academia of Taiwan: A interview with Dr. Chun-Yen Chang

B.J. Sheu, 1999, IEEE Circuits and Devices Magazine.

Mr. Silicon Chips of Taiwan: An Interview with Chung-Yu Wu

Y. Oshima, B.J. Sheu, S.H. Jen, 1997, IEEE Circuits and Devices Magazine.

Accurate MOS Transistor Modeling and Parameter Extraction Valid up to 10 GHz

M. Schroter, C. Enz, B.J. Sheu, 1998, 28th European Solid-State Device Research Conference.

A new method to determine effective channel widths of MOS transistors for VLSI device design

C.-P. Wan, B.J. Sheu, H. Yang, 1990, International Conference on Microelectronic Test Structures.