Julien Vial

Is triple modular redundancy suitable for yield improvement?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009, IET Comput. Digit. Tech..

SoC Yield Improvement: Redundant Architectures to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Test Conference.

Is TMR Suitable for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009 .

SoC Yield Improvement for Future Nanoscale Technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, ETS 2009.

Yield Improvement, Fault-Tolerance to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Motor vehicle seat comprising a cushion insert overmold for its rotational mounting

Laurent Georges, Julien Vial, Laurence Davergne, 2008 .

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Using TMR Architectures for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.