Fengwei An

发表

A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression. Appl. Sci. 2017, 7, 1106

Zunkai Huang, Dai Suzuki, Xiangyu Zhang, 2019, Applied Sciences.

Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction

Fengwei An, Xiangyu Zhang, Yuki Fujita, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign

Fengwei An, Hans Jürgen Mattausch, 2012, 2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies.

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization

Fengwei An, Xiangyu Zhang, Lei Chen, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression

Zunkai Huang, Yongxin Zhu, Fengwei An, 2017 .

Multi-port SRAM with Multi-bank for Self-organizing Maps Neural Network (Invited paper)

Fengwei An, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Real-time hybrid learning and recognition system with software-hardware cooperation

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide, 2011, 2011 IEEE International Conference on Robotics and Biomimetics.

VLSI realization of learning vector quantization with hardware/software co-design for different applications

Fengwei An, Hans Jurgen Mattausch, Lei Chen, 2015 .

LVQ neural network SoC adaptable to different on-chip learning and recognition applications

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A SoPC architecture for nearest-neighbor based learning and recognition

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2014, 2014 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS

Fengwei An, Xiangyu Zhang, Aiwen Luo, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration

Fengwei An, Xiangyu Zhang, Lei Chen, 2016, IEEE Transactions on Multi-Scale Computing Systems.

Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Object-recognition VLSI for pedestrian detection in automotive applications

Fengwei An, Xiangyu Zhang, Lei Chen, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier

Fengwei An, Xiangyu Zhang, Aiwen Luo, 2019, IEEE Access.

SoC Realization of LVQ Neural Network with On-chip Learning and Recognition

Lei Chen, Fengwei An, Hans Jurgen Mattausch, 2014 .

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2016, IEICE Trans. Electron..

Memory-based hardware-accelerated system for high-speed human detection

Fengwei An, Hans Jürgen Mattausch, Indra Bagus Wicaksono, 2014, Adv. Robotics.

A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space

Fengwei An, Xiangyu Zhang, Aiwen Luo, 2018, IEEE Transactions on Circuits and Systems for Video Technology.

Human recognition with a hardware-accelerated multi-prototype learning and classification system

Fengwei An, Hans Jürgen Mattausch, Indra Bagus Wicaksono, 2012, 2012 IEEE International Conference on Robotics and Biomimetics (ROBIO).

Low-power and real-time computer vision on-chip

Fengwei An, Hao Yu, Wei Pang, 2016, 2016 International SoC Design Conference (ISOCC).

A Hardware-Accelerated Reduced Dimensionality Multi-Prototype Learning and Recognition System with complementary classifiers

Fengwei An, Hans Jurgen Mattausch, Indra Bagus Wicaksono, 2013, 2013 IEEE Conference on Cybernetics and Intelligent Systems (CIS).

K-means clustering algorithm for multimedia applications with flexible HW/SW co-design

Fengwei An, Hans Jürgen Mattausch, 2013, J. Syst. Archit..

Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm

Fengwei An, Hans Jurgen Mattausch, Xiangyu Zhang, 2019, IEICE Trans. Inf. Syst..

Flexible feature-space-construction architecture and its VLSI implementation for multi-scale object detection

Fengwei An, Xiangyu Zhang, Lei Chen, 2018 .

K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture

Fengwei An, Hans Jurgen Mattausch, Lei Chen, 2016 .

Highly flexible nearest-neighbor-search associative memory with integrated k nearest neighbor classifier, configurable parallelism and dual-storage space

Fengwei An, Hans Jurgen Mattausch, Lei Chen, 2016 .

Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures

Fengwei An, Xiangyu Zhang, Lei Chen, 2017, Sensors.

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide, 2012, IEICE Trans. Inf. Syst..

A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor

Zunkai Huang, Yongxin Zhu, Fengwei An, 2017, IEEE Access.

An FPGA-implemented Associative-memory Based Online Learning Method

Fengwei An, Hans Jurgen Mattausch, Tetsushi Koide, 2011 .

A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection

Fengwei An, Hao Yu, Wei Mao, 2022, IEEE Design & Test.

Parallel-elementary-stream architecture for nearest-neighbor-search-based self-organizing map

Fengwei An, Xiangyu Zhang, Lei Chen, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition

Fengwei An, Xiangyu Zhang, Lei Chen, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture

Fengwei An, Hans Jurgen Mattausch, Xiangyu Zhang, 2017 .

A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots

Fengwei An, Chao Wang, Guoyi Yu, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Low Computation and High Efficiency Sobel Edge Detector for Robot Vision

Fengwei An, Chao Wang, Guoyi Yu, 2021, 2021 IEEE International Conference on Real-time Computing and Robotics (RCAR).

A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application

Fengwei An, Lei Chen, Pingcheng Dong, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.