Morimoto Masao

A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation

Komatsu Shigenobu, Yamaoka Masanao, Morimoto Masao, 2010 .

Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition

Taki Kazuo, Nagata Makoto, Morimoto Masao, 2005 .

A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time

Tanaka Shinji, Morimoto Masao, Nii Koji, 2017 .

20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists

Morimoto Masao, Nii Koji, Yabuuchi Makoto, 2015 .

Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator

Tanaka Koji, Komatsu Shigenobu, Morimoto Masao, 2013 .