Shen-Fu Hsiao

发表

A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation

Shen-Fu Hsiao, Wei-Ren Shiue, 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen, 2008, 2008 IEEE International Symposium on Circuits and Systems.

VLSI implementation of the quadratic-spline W-transform for multi-resolution image processing

Shen-Fu Hsiao, 1998 .

Low-error carry-free fixed-width multipliers with low-cost compensation circuits

Shen-Fu Hsiao, Tso-Bing Juang, 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding

Shen-Fu Hsiao, Hou-Jen Ko, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

High-radix low-complexity architectures for long-length DCT using conventional arithmetic and ROM-based distributed arithmetic

Shen-Fu Hsiao, Yu-Hen Hu, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Hierarchical Multipartite Function Evaluation

Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, 2017, IEEE Transactions on Computers.

Adaptive Jacobi method for parallel singular value decompositions

Shen-Fu Hsiao, 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels

Shen-Fu Hsiao, Chen-Yen Tsai, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations

Shen-Fu Hsiao, Hsuan-Jui Chang, 2020, ISCAS.

A cost-efficient and fully-pipelinable architecture for DCT/IDCT

Shen-Fu Hsiao, Wei-Ren Shiue, Jian-Ming Tseng, 1999, IEEE Trans. Consumer Electron..

A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation

Shen-Fu Hsiao, Wen-Liang Huang, Hou-Jen Ko, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Compression of Lookup Table for Piecewise Polynomial Function Evaluation

Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu, 2014, 2014 17th Euromicro Conference on Digital System Design.

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics

Ing-Jer Huang, Liang-Bi Chen, Chien-Chou Wang, 2009, 2009 Asia and South Pacific Design Automation Conference.

Direct implementation of 2-D DCT on a low-cost linear-array architecture without intermediate transpose memory

Shen-Fu Hsiao, Jian-Ming Tseng, 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning

Shen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen, 2014, 2014 17th Euromicro Conference on Digital System Design.

Architectural Optimization for the forward and Inverse MixColumn Operations in Rijndael AES

Ming-Chih Chen, Shen-Fu Hsiao, Ming-Yu Tsai, 2003 .

Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation

Shen-Fu Hsiao, Chia-Yang Wong, Yu-Chang Chen, 2020, ISCAS.

Design of a low-cost floating-point programmable vertex processor for mobile graphics applications based on hybrid number system

Shen-Fu Hsiao, Chia-Sheng Wen, Chan-Feng Chiu, 2011, 2011 IEEE International Conference on IC Design & Technology.

A hybrid W-transform-based coding and its VLSI realization for image compression

Shen-Fu Hsiao, Wen-Chen Huang, Chung-Nan Lee, 1998 .

Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks

Shen-Fu Hsiao, Kuey-Chin Huang, Yu-Hong Chen, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Householder CORDIC Algorithms

Shen-Fu Hsiao, Jean-Marc Delosme, J. Delosme, 1995, IEEE Trans. Computers.

A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics

Ing-Jer Huang, Ming-Chao Chiang, Shen-Fu Hsiao, 2007, 2007 IEEE International Symposium on Consumer Electronics.

The CORDIC Householder algorithm

Shen-Fu Hsiao, Jean-Marc Delosme, J. Delosme, 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property design

Yu Hen Hu, Shen-Fu Hsiao, Cheng-Han Lee, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-cost designs of rectangular to polar coordinate converters for digital communication

Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping

Shen-Fu Hsiao, Chia-Sheng Wen, Yu-Ling Tseng, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TWO EFFIclENTAREA REDUCITON METHODS FOR IMPLEIVESTATIONS OF THERJJNDAELADVANCFLDENCRYPTIONSTANDARD

Shen-Fu Hsiao, Ming-Chih Chen, 2004 .

Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology

Chua-Chin Wang, Shen-Fu Hsiao, Chuan-Lin Wu, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

VLSI implementations of stereo matching using Dynamic Programming

Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

Low-power dual-precision table-based function evaluation supporting dynamic precision changes

Shen-Fu Hsiao, Kuei-Chun Huang, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Novel memory organization and circuit designs for efficient data access in applications of 3D graphics and multimedia coding

Shen-Fu Hsiao, Ming-Yu Tsai, Yo-Chi Chen, 2006, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06).

Efficient designs of flaoting-point CORDIC rotation and vectoring operations

Shen-Fu Hsiao, Ming-Yu Tsai, Hsin-Mau Lee, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics

Ing-Jer Huang, Chien-Chou Wang, Jin-Hua Hong, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard

Ming-Chih Chen, Shen-Fu Hsiao, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Low-cost design of reciprocal function units using shared multipliers and adders for polynomial approximation and Newton Raphson interpolation

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen, 2010, 2010 International Symposium on Next Generation Electronics.

Low-power and high-performance design of OpenGL ES 2.0 graphics processing unit for mobile applications

Shen-Fu Hsiao, Kai-Hsiang Tsao, Shang-Yu Li, 2015, 2015 IEEE International Conference on Digital Signal Processing (DSP).

New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array

Shen-Fu Hsiao, Wei-Ren Shiue, 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD

Shen-Fu Hsiao, Jean-Marc Delosme, Chun-Yi Lau, 2000, J. VLSI Signal Process..

Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks

Shen-Fu Hsiao, Yu-Chang Chen, Hsiang-Hao Liang, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Hardware design of histograms of oriented gradients based on local binary pattern and binarization

Shen-Fu Hsiao, Ching-Hui Wang, Jun-Mao Chan, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions

Shen-Fu Hsiao, Chia-Sheng Wen, Hou-Jen Ko, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

New unified VLSI architectures for computing DFT and other transforms

Shen-Fu Hsiao, Chung-Yi Yen, 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic

Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen, 2002, VLSI Design.

Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations

Ming-Chih Chen, Shen-Fu Hsiao, Chia-Shin Tu, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

A nearly constant delay and low power VLSI design of a pipeline Reed–Solomon encoder for storage and communication systems

Shen-Fu Hsiao, Yan-Haw Chen, Trieu-Kien Truong, 2013 .

Power, speed and area comparison of several new DPT architectures

Shen-Fu Hsiao, Chung-Yi Yen, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Low-cost unified architectures for the computation of discrete trigonometric transforms

Shen-Fu Hsiao, Wei-Ren Shiue, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

System-on-chip implementation of the whole advanced encryption standard processor using reduced XOR-based sum-of-product operations

Ming-Chih Chen, Shen-Fu Hsiao, C.-C. Lin, 2005 .

Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling

Shen-Fu Hsiao, Wen-Ling Wang, Guan-Fu Yeh, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array

Shen-Fu Hsiao, Wei-Ren Shiue, 2001, IEEE Trans. Circuits Syst. Video Technol..

Low-Complexity Deep Neural Networks for Image Object Classification and Detection

Shen-Fu Hsiao, Chih-Chien Lin, Jing-Fu Zhan, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system

Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations

Shen-Fu Hsiao, Kun-Chih Chen, Chih-Chien Lin, 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Design and implementation of a video-oriented network-interface-card system

Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang, 2003, ASP-DAC '03.

Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication

Shen-Fu Hsiao, Yu-Hong Chen, Shen-Fu Hsiao, 2020, 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Implementation of floating-point CORDIC rotation and vectoring based on look up tables and multipliers

Shen-Fu Hsiao, Hsin-Mau Lee, Chia-Shen Wen, 2010, 2010 International Symposium on Next Generation Electronics.

Table-Based Circuits for DSP Applications

Shen-Fu Hsiao, Pramod Kumar Meher, Shen-Fu Hsiao, 2017 .

Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation

Shen-Fu Hsiao, Kun-Chih Chen, Yuan-Nan Chang, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking

Shen-Fu Hsiao, Kai-Hsiang Chang, Yor-Chin Tai, 2000, IEEE Trans. Consumer Electron..

Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method

Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

An Automatic Cache Generator Based on Content-Addressable Memory

Shen-Fu Hsiao, Ming-Yu Tsai, Tze-Chong Cheng, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm

Ming-Chih Chen, Shen-Fu Hsiao, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A high performance function generator for multiplier-based arithmetic operations

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Design of low-leakage multi-port SRAM for register file in graphics processing unit

Shen-Fu Hsiao, Pu-Cheng Wu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of a CORDIC-based SIN/COS intellectual property (IP) using predictable sign bits

Shen-Fu Hsiao, Tso-Pin Chuang, Chao-Chuan Huang, 2001, Proceedings of the 27th European Solid-State Circuits Conference.

Transistor sizing and layout merging of basic cells in pass transistor logic cell library

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Para-CORDIC: parallel CORDIC rotation algorithm

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units

Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms

Shen-Fu Hsiao, Jean-Marc Delosme, 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2005, IEICE Trans. Inf. Syst..

Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators

Shen-Fu Hsiao, Pei-Hsuen Wu, Shen-Fu Hsiao, 2018, 2018 IEEE 7th Global Conference on Consumer Electronics (GCCE).

Vlsi Implementation Of A High-throughput Cordic Processor For Both Angle Calculation And Vector Rotation

Shen-Fu Hsiao, Jen-Yin Chen, Shen-Fu Hsiao, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

VLSI implementation of digit-recurrent CORDIC with constant scaling factor

Shen-Fu Hsiao, Jen-Yin Chen, Shen-Fu Hsiao, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations

Yu Hen Hu, Shen-Fu Hsiao, Tso-Bing Juang, 2004, IEEE Signal Process. Lett..

Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse

Shen-Fu Hsiao, Pei-Hsuan Wu, Jien-Min Chen, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation

Shen-Fu Hsiao, Pramod Kumar Meher, Chia-Sheng Wen, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

VLSI implementation of belief-propagation-based stereo matching with linear-model message update

Shen-Fu Hsiao, Po-Sheng Wu, Jun-Ming Huang, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures

Shen-Fu Hsiao, Andrew Lee, Cheng-Han Lee, 2011, 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR).

High-performance multiplexer-based logic synthesis using pass-transistor logic

Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation

Ming-Chih Chen, Shen-Fu Hsiao, Jun-Hong Zhang Jian, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hardware efficient implementation of histograms of oriented gradients for pedestrian detection

Shen-Fu Hsiao, Tz-Heng Tz-Heng You, 2017, 2017 IEEE 6th Global Conference on Consumer Electronics (GCCE).

Top-down logic design with pass-transistor cells and efficient synthesiser

Shen-Fu Hsiao, Jia-Siang Yeh, 1998 .

Automatic generation of high-performance multiple-input XOR/XNOR circuits and its application in Advanced Encryption Standard (AES)

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen, 2010, 2010 International Symposium on Next Generation Electronics.

Discussions on the CORDIC processor using leading zeros detector

Shen-Fu Hsiao, Tso-Bing Juang, 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

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Yun-Nan Chang, Shen-Fu Hsiao, Kai-Hsiang Tsao, 2015 .

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches

Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin, 2008, 2008 IEEE International Symposium on Circuits and Systems.

An efficient synthesizer for generation of fast parallel multipliers

Shen-Fu Hsiao, Ming-Rong Jiang, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Hardware design of disparity computation for stereo vision using guided image filtering

Shen-Fu Hsiao, Chih-Hsuan Chang, Shen-Fu Hsiao, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support

Chun-Hung Lai, Ing-Jer Huang, Shiann-Rong Kuang, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Optimization of Lookup Table Size in Table-Bound Design of Function Computation

Shen-Fu Hsiao, Kun-Chih Chen, Yi-Hau Chen, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure

Shen-Fu Hsiao, Jen-Yin Chen, Shen-Fu Hsiao, 1998, J. VLSI Signal Process..

A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations

Shen-Fu Hsiao, Shen-Fu Hsiao, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec

Shen-Fu Hsiao, Jian-Ming Tseng, 2001, J. VLSI Signal Process..

Partition methodology for the final adder in a tree-structure parallel multiplier generator

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2002, Asia-Pacific Conference on Circuits and Systems.

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

Ming-Chih Chen, Shen-Fu Hsiao, Ming-Yu Tsai, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Parallel singular value decomposition of complex matrices using multidimensional CORDIC algorithms

Shen-Fu Hsiao, Jean-Marc Delosme, J. Delosme, 1996, IEEE Trans. Signal Process..

Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage

Shen-Fu Hsiao, Jyun-Liang Chen, Yi Hsu, 2021, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW).

Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation

Shen-Fu Hsiao, Yi Hsu, Jian-Ming Chen, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models

Shen-Fu Hsiao, Bo-Ching Tsai, 2021, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW).

Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning

Shen-Fu Hsiao, Yu-Chang Chen, Yu-Che Yen, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log2 N

Shen-Fu Hsiao, W.-R. Shiue, J.-M. Tseng, 2000 .

Design of low-cost and high-throughput linear arrays for DFT computations: algorithms, architectures, and implementations

Shen-Fu Hsiao, Wei-Ren Shiue, 2000 .