Paulo Centoducatte

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Design of a Decompressor Engine on a SPARC Processor

Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2001, CASES '01.

An open-source binary utility generator

Paulo Centoducatte, Alexandro Baldassin, Luiz Cláudio Villar dos Santos, 2008, TODE.

Code compression based on operand factorization

Guido Araujo, Paulo Centoducatte, Ricardo Pannain, 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

Extending the ArchC language for automatic generation of assemblers

Paulo Centoducatte, Alexandro Baldassin, Sandro Rigo, 2005, 17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05).

Compressed code execution on DSP architectures

Guido Araujo, Paulo Centoducatte, Ricardo Pannain, 1999, Proceedings 12th International Symposium on System Synthesis.

Expression-tree-based algorithms for code compression on embedded RISC architectures

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Multi-profile based code compression

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2004, Proceedings. 41st Design Automation Conference, 2004..

Using multiple abstraction levels to speedup an MPSoC virtual platform simulator

Rodolfo Azevedo, Paulo Centoducatte, Alexandro Baldassin, 2011, 2011 22nd IEEE International Symposium on Rapid System Prototyping.

STM versus lock-based systems: An energy consumption perspective

Rodolfo Azevedo, Paulo Centoducatte, Alexandro Baldassin, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Teaching computer architecture using an architecture description language

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2004, WCAE '04.

Multi-profile instruction based compression

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2004, 16th Symposium on Computer Architecture and High Performance Computing.

A Software Transactional Memory System for an Asymmetric Processor Architecture

Rodolfo Azevedo, Paulo Centoducatte, Alexandro Baldassin, 2008, 2008 20th International Symposium on Computer Architecture and High Performance Computing.

Automatic Retargeting of Binary Utilities for Embedded Code Generation

Paulo Centoducatte, Alexandro Baldassin, Luiz Cláudio Villar dos Santos, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

SPARC16: A New Compression Approach for the SPARC Architecture

Eduardo C. Xavier, Rodolfo Azevedo, Paulo Centoducatte, 2009, 2009 21st International Symposium on Computer Architecture and High Performance Computing.

Characterizing the Energy Consumption of Software Transactional Memory

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2009, IEEE Computer Architecture Letters.

A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

On the energy-efficiency of software transactional memory

Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, 2009, SBCCI.

ACCGen: An Automatic ArchC Compiler Generator

Paulo Centoducatte, Edson Borin, Rafael Auler, 2012, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing.