Tomoyuki Kodama

Architecture for High Speed Evolutionary Computation

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2003 .

Architecture for high‐speed evolutionary computation

Hidekazu Terai, Masaya Yoshikawa, Tetsuya Imai, 2004 .

Development of processor cores for digital consumer appliances

Tetsuya Yamada, Fumio Arakawa, Takashi Okada, 2006 .

Transparent SOC: on-chip analyzing techniques and implementation for embedded processor

Fumio Arakawa, Makoto Saen, Junichi Nishimoto, 2004, IEEE International SOC Conference, 2004. Proceedings..

Development of processor cores for digital consumer appliances

Tetsuya Yamada, Fumio Arakawa, Takashi Okada, 2006, Systems and Computers in Japan.

SoC debug architecture and applications

Fumio Arakawa, Makoto Saen, Junichi Nishimoto, 2004 .

An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

Fumio Arakawa, Takahiro Irita, Tatsuya Kamei, 2004 .

Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration

Kenichi Osada, Hiroyuki Mizuno, Makoto Saen, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).